ETRAX: Simplify the interrupt controller model.

[qemu.git] / hw / pl011.c

diff --git a/hw/pl011.c b/hw/pl011.c
index 29e551ad8b722d5185b0087ce79cedc626283810..468d48a9269dd3e4e6eb017f4b2ee465a57073e8 100644 (file)
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * Arm PrimeCell PL011 UART
  *
  * Copyright (c) 2006 CodeSourcery.
@@ -7,10 +7,11 @@
  * This code is licenced under the GPL.
  */
 
-#include "vl.h"
+#include "hw.h"
+#include "qemu-char.h"
+#include "primecell.h"
 
 typedef struct {
-    uint32_t base;
     uint32_t readbuff;
     uint32_t flags;
     uint32_t lcr;
@@ -28,6 +29,7 @@ typedef struct {
     int read_trigger;
     CharDriverState *chr;
     qemu_irq irq;
+    enum pl011_type type;
 } pl011_state;
 
 #define PL011_INT_TX 0x20
@@ -38,13 +40,15 @@ typedef struct {
 #define PL011_FLAG_TXFF 0x20
 #define PL011_FLAG_RXFE 0x10
 
-static const unsigned char pl011_id[] =
-{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
+static const unsigned char pl011_id[2][8] = {
+  { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_ARM */
+  { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_LUMINARY */
+};
 
 static void pl011_update(pl011_state *s)
 {
     uint32_t flags;
-    
+
     flags = s->int_level & s->int_enabled;
     qemu_set_irq(s->irq, flags != 0);
 }
@@ -54,9 +58,8 @@ static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
     pl011_state *s = (pl011_state *)opaque;
     uint32_t c;
 
-    offset -= s->base;
     if (offset >= 0xfe0 && offset < 0x1000) {
-        return pl011_id[(offset - 0xfe0) >> 2];
+        return pl011_id[s->type][(offset - 0xfe0) >> 2];
     }
     switch (offset >> 2) {
     case 0: /* UARTDR */
@@ -73,6 +76,7 @@ static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
         if (s->read_count == s->read_trigger - 1)
             s->int_level &= ~ PL011_INT_RX;
         pl011_update(s);
+        qemu_chr_accept_input(s->chr);
         return c;
     case 1: /* UARTCR */
         return 0;
@@ -99,7 +103,7 @@ static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
     case 18: /* UARTDMACR */
         return s->dmacr;
     default:
-        cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -124,7 +128,6 @@ static void pl011_write(void *opaque, target_phys_addr_t offset,
     pl011_state *s = (pl011_state *)opaque;
     unsigned char ch;
 
-    offset -= s->base;
     switch (offset >> 2) {
     case 0: /* UARTDR */
         /* ??? Check if transmitter is enabled.  */
@@ -137,6 +140,9 @@ static void pl011_write(void *opaque, target_phys_addr_t offset,
     case 1: /* UARTCR */
         s->cr = value;
         break;
+    case 6: /* UARTFR */
+        /* Writes to Flag register are ignored.  */
+        break;
     case 8: /* UARTUARTILPR */
         s->ilpr = value;
         break;
@@ -172,11 +178,11 @@ static void pl011_write(void *opaque, target_phys_addr_t offset,
             cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
         break;
     default:
-        cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
     }
 }
 
-static int pl011_can_recieve(void *opaque)
+static int pl011_can_receive(void *opaque)
 {
     pl011_state *s = (pl011_state *)opaque;
 
@@ -186,7 +192,7 @@ static int pl011_can_recieve(void *opaque)
         return s->read_count < 1;
 }
 
-static void pl011_recieve(void *opaque, const uint8_t *buf, int size)
+static void pl011_put_fifo(void *opaque, uint32_t value)
 {
     pl011_state *s = (pl011_state *)opaque;
     int slot;
@@ -194,7 +200,7 @@ static void pl011_recieve(void *opaque, const uint8_t *buf, int size)
     slot = s->read_pos + s->read_count;
     if (slot >= 16)
         slot -= 16;
-    s->read_fifo[slot] = *buf;
+    s->read_fifo[slot] = value;
     s->read_count++;
     s->flags &= ~PL011_FLAG_RXFE;
     if (s->cr & 0x10 || s->read_count == 16) {
@@ -206,9 +212,15 @@ static void pl011_recieve(void *opaque, const uint8_t *buf, int size)
     }
 }
 
+static void pl011_receive(void *opaque, const uint8_t *buf, int size)
+{
+    pl011_put_fifo(opaque, *buf);
+}
+
 static void pl011_event(void *opaque, int event)
 {
-    /* ??? Should probably implement break.  */
+    if (event == CHR_EVENT_BREAK)
+        pl011_put_fifo(opaque, 0x400);
 }
 
 static CPUReadMemoryFunc *pl011_readfn[] = {
@@ -223,8 +235,59 @@ static CPUWriteMemoryFunc *pl011_writefn[] = {
    pl011_write
 };
 
+static void pl011_save(QEMUFile *f, void *opaque)
+{
+    pl011_state *s = (pl011_state *)opaque;
+    int i;
+
+    qemu_put_be32(f, s->readbuff);
+    qemu_put_be32(f, s->flags);
+    qemu_put_be32(f, s->lcr);
+    qemu_put_be32(f, s->cr);
+    qemu_put_be32(f, s->dmacr);
+    qemu_put_be32(f, s->int_enabled);
+    qemu_put_be32(f, s->int_level);
+    for (i = 0; i < 16; i++)
+        qemu_put_be32(f, s->read_fifo[i]);
+    qemu_put_be32(f, s->ilpr);
+    qemu_put_be32(f, s->ibrd);
+    qemu_put_be32(f, s->fbrd);
+    qemu_put_be32(f, s->ifl);
+    qemu_put_be32(f, s->read_pos);
+    qemu_put_be32(f, s->read_count);
+    qemu_put_be32(f, s->read_trigger);
+}
+
+static int pl011_load(QEMUFile *f, void *opaque, int version_id)
+{
+    pl011_state *s = (pl011_state *)opaque;
+    int i;
+
+    if (version_id != 1)
+        return -EINVAL;
+
+    s->readbuff = qemu_get_be32(f);
+    s->flags = qemu_get_be32(f);
+    s->lcr = qemu_get_be32(f);
+    s->cr = qemu_get_be32(f);
+    s->dmacr = qemu_get_be32(f);
+    s->int_enabled = qemu_get_be32(f);
+    s->int_level = qemu_get_be32(f);
+    for (i = 0; i < 16; i++)
+        s->read_fifo[i] = qemu_get_be32(f);
+    s->ilpr = qemu_get_be32(f);
+    s->ibrd = qemu_get_be32(f);
+    s->fbrd = qemu_get_be32(f);
+    s->ifl = qemu_get_be32(f);
+    s->read_pos = qemu_get_be32(f);
+    s->read_count = qemu_get_be32(f);
+    s->read_trigger = qemu_get_be32(f);
+
+    return 0;
+}
+
 void pl011_init(uint32_t base, qemu_irq irq,
-                CharDriverState *chr)
+                CharDriverState *chr, enum pl011_type type)
 {
     int iomemtype;
     pl011_state *s;
@@ -232,18 +295,17 @@ void pl011_init(uint32_t base, qemu_irq irq,
     s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
     iomemtype = cpu_register_io_memory(0, pl011_readfn,
                                        pl011_writefn, s);
-    cpu_register_physical_memory(base, 0x00000fff, iomemtype);
-    s->base = base;
+    cpu_register_physical_memory(base, 0x00001000, iomemtype);
     s->irq = irq;
+    s->type = type;
     s->chr = chr;
     s->read_trigger = 1;
     s->ifl = 0x12;
     s->cr = 0x300;
     s->flags = 0x90;
-    if (chr){ 
-        qemu_chr_add_handlers(chr, pl011_can_recieve, pl011_recieve,
+    if (chr){
+        qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
                               pl011_event, s);
     }
-    /* ??? Save/restore.  */
+    register_savevm("pl011_uart", -1, 1, pl011_save, pl011_load, s);
 }
-