*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/pci/msi.h"
-#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
+#include "migration/vmstate.h"
#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/module.h"
#include "sysemu/block-backend.h"
#include "sysemu/dma.h"
#include "hw/ide/internal.h"
#include "hw/ide/pci.h"
-#include "hw/ide/ahci_internal.h"
+#include "ahci_internal.h"
-#define DEBUG_AHCI 0
-
-#define DPRINTF(port, fmt, ...) \
-do { \
- if (DEBUG_AHCI) { \
- fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \
- fprintf(stderr, fmt, ## __VA_ARGS__); \
- } \
-} while (0)
+#include "trace.h"
static void check_cmd(AHCIState *s, int port);
static int handle_cmd(AHCIState *s, int port, uint8_t slot);
static void ahci_unmap_clb_address(AHCIDevice *ad);
static void ahci_unmap_fis_address(AHCIDevice *ad);
+static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = {
+ [AHCI_HOST_REG_CAP] = "CAP",
+ [AHCI_HOST_REG_CTL] = "GHC",
+ [AHCI_HOST_REG_IRQ_STAT] = "IS",
+ [AHCI_HOST_REG_PORTS_IMPL] = "PI",
+ [AHCI_HOST_REG_VERSION] = "VS",
+ [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL",
+ [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS",
+ [AHCI_HOST_REG_EM_LOC] = "EM_LOC",
+ [AHCI_HOST_REG_EM_CTL] = "EM_CTL",
+ [AHCI_HOST_REG_CAP2] = "CAP2",
+ [AHCI_HOST_REG_BOHC] = "BOHC",
+};
-static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
+static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = {
+ [AHCI_PORT_REG_LST_ADDR] = "PxCLB",
+ [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU",
+ [AHCI_PORT_REG_FIS_ADDR] = "PxFB",
+ [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU",
+ [AHCI_PORT_REG_IRQ_STAT] = "PxIS",
+ [AHCI_PORT_REG_IRQ_MASK] = "PXIE",
+ [AHCI_PORT_REG_CMD] = "PxCMD",
+ [7] = "Reserved",
+ [AHCI_PORT_REG_TFDATA] = "PxTFD",
+ [AHCI_PORT_REG_SIG] = "PxSIG",
+ [AHCI_PORT_REG_SCR_STAT] = "PxSSTS",
+ [AHCI_PORT_REG_SCR_CTL] = "PxSCTL",
+ [AHCI_PORT_REG_SCR_ERR] = "PxSERR",
+ [AHCI_PORT_REG_SCR_ACT] = "PxSACT",
+ [AHCI_PORT_REG_CMD_ISSUE] = "PxCI",
+ [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF",
+ [AHCI_PORT_REG_FIS_CTL] = "PxFBS",
+ [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP",
+ [18 ... 27] = "Reserved",
+ [AHCI_PORT_REG_VENDOR_1 ...
+ AHCI_PORT_REG_VENDOR_4] = "PxVS",
+};
+
+static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = {
+ [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
+ [AHCI_PORT_IRQ_BIT_PSS] = "PSS",
+ [AHCI_PORT_IRQ_BIT_DSS] = "DSS",
+ [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS",
+ [AHCI_PORT_IRQ_BIT_UFS] = "UFS",
+ [AHCI_PORT_IRQ_BIT_DPS] = "DPS",
+ [AHCI_PORT_IRQ_BIT_PCS] = "PCS",
+ [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS",
+ [8 ... 21] = "RESERVED",
+ [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS",
+ [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS",
+ [AHCI_PORT_IRQ_BIT_OFS] = "OFS",
+ [25] = "RESERVED",
+ [AHCI_PORT_IRQ_BIT_INFS] = "INFS",
+ [AHCI_PORT_IRQ_BIT_IFS] = "IFS",
+ [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS",
+ [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS",
+ [AHCI_PORT_IRQ_BIT_TFES] = "TFES",
+ [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
+};
+
+static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
{
uint32_t val;
- AHCIPortRegs *pr;
- pr = &s->dev[port].port_regs;
+ AHCIPortRegs *pr = &s->dev[port].port_regs;
+ enum AHCIPortReg regnum = offset / sizeof(uint32_t);
+ assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
- switch (offset) {
- case PORT_LST_ADDR:
+ switch (regnum) {
+ case AHCI_PORT_REG_LST_ADDR:
val = pr->lst_addr;
break;
- case PORT_LST_ADDR_HI:
+ case AHCI_PORT_REG_LST_ADDR_HI:
val = pr->lst_addr_hi;
break;
- case PORT_FIS_ADDR:
+ case AHCI_PORT_REG_FIS_ADDR:
val = pr->fis_addr;
break;
- case PORT_FIS_ADDR_HI:
+ case AHCI_PORT_REG_FIS_ADDR_HI:
val = pr->fis_addr_hi;
break;
- case PORT_IRQ_STAT:
+ case AHCI_PORT_REG_IRQ_STAT:
val = pr->irq_stat;
break;
- case PORT_IRQ_MASK:
+ case AHCI_PORT_REG_IRQ_MASK:
val = pr->irq_mask;
break;
- case PORT_CMD:
+ case AHCI_PORT_REG_CMD:
val = pr->cmd;
break;
- case PORT_TFDATA:
+ case AHCI_PORT_REG_TFDATA:
val = pr->tfdata;
break;
- case PORT_SIG:
+ case AHCI_PORT_REG_SIG:
val = pr->sig;
break;
- case PORT_SCR_STAT:
+ case AHCI_PORT_REG_SCR_STAT:
if (s->dev[port].port.ifs[0].blk) {
val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
val = SATA_SCR_SSTATUS_DET_NODEV;
}
break;
- case PORT_SCR_CTL:
+ case AHCI_PORT_REG_SCR_CTL:
val = pr->scr_ctl;
break;
- case PORT_SCR_ERR:
+ case AHCI_PORT_REG_SCR_ERR:
val = pr->scr_err;
break;
- case PORT_SCR_ACT:
+ case AHCI_PORT_REG_SCR_ACT:
val = pr->scr_act;
break;
- case PORT_CMD_ISSUE:
+ case AHCI_PORT_REG_CMD_ISSUE:
val = pr->cmd_issue;
break;
- case PORT_RESERVED:
default:
+ trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum],
+ offset);
val = 0;
}
- DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
- return val;
+ trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val);
+ return val;
}
-static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
+static void ahci_irq_raise(AHCIState *s)
{
DeviceState *dev_state = s->container;
PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
TYPE_PCI_DEVICE);
- DPRINTF(0, "raise irq\n");
+ trace_ahci_irq_raise(s);
if (pci_dev && msi_enabled(pci_dev)) {
msi_notify(pci_dev, 0);
}
}
-static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
+static void ahci_irq_lower(AHCIState *s)
{
DeviceState *dev_state = s->container;
PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
TYPE_PCI_DEVICE);
- DPRINTF(0, "lower irq\n");
+ trace_ahci_irq_lower(s);
if (!pci_dev || !msi_enabled(pci_dev)) {
qemu_irq_lower(s->irq);
static void ahci_check_irq(AHCIState *s)
{
int i;
-
- DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus);
+ uint32_t old_irq = s->control_regs.irqstatus;
s->control_regs.irqstatus = 0;
for (i = 0; i < s->ports; i++) {
s->control_regs.irqstatus |= (1 << i);
}
}
-
+ trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus);
if (s->control_regs.irqstatus &&
(s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
- ahci_irq_raise(s, NULL);
+ ahci_irq_raise(s);
} else {
- ahci_irq_lower(s, NULL);
+ ahci_irq_lower(s);
}
}
static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
- int irq_type)
+ enum AHCIPortIRQ irqbit)
{
- DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
- irq_type, d->port_regs.irq_mask & irq_type);
+ g_assert((unsigned)irqbit < 32);
+ uint32_t irq = 1U << irqbit;
+ uint32_t irqstat = d->port_regs.irq_stat | irq;
- d->port_regs.irq_stat |= irq_type;
+ trace_ahci_trigger_irq(s, d->port_no,
+ AHCIPortIRQ_lookup[irqbit], irq,
+ d->port_regs.irq_stat, irqstat,
+ irqstat & d->port_regs.irq_mask);
+
+ d->port_regs.irq_stat = irqstat;
ahci_check_irq(s);
}
return 0;
}
-static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
+static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
{
AHCIPortRegs *pr = &s->dev[port].port_regs;
+ enum AHCIPortReg regnum = offset / sizeof(uint32_t);
+ assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
+ trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val);
- DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
- switch (offset) {
- case PORT_LST_ADDR:
- pr->lst_addr = val;
- break;
- case PORT_LST_ADDR_HI:
- pr->lst_addr_hi = val;
- break;
- case PORT_FIS_ADDR:
- pr->fis_addr = val;
- break;
- case PORT_FIS_ADDR_HI:
- pr->fis_addr_hi = val;
- break;
- case PORT_IRQ_STAT:
- pr->irq_stat &= ~val;
- ahci_check_irq(s);
- break;
- case PORT_IRQ_MASK:
- pr->irq_mask = val & 0xfdc000ff;
- ahci_check_irq(s);
- break;
- case PORT_CMD:
- /* Block any Read-only fields from being set;
- * including LIST_ON and FIS_ON.
- * The spec requires to set ICC bits to zero after the ICC change
- * is done. We don't support ICC state changes, therefore always
- * force the ICC bits to zero.
- */
- pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
- (val & ~(PORT_CMD_RO_MASK|PORT_CMD_ICC_MASK));
-
- /* Check FIS RX and CLB engines */
- ahci_cond_start_engines(&s->dev[port]);
-
- /* XXX usually the FIS would be pending on the bus here and
- issuing deferred until the OS enables FIS receival.
- Instead, we only submit it once - which works in most
- cases, but is a hack. */
- if ((pr->cmd & PORT_CMD_FIS_ON) &&
- !s->dev[port].init_d2h_sent) {
- ahci_init_d2h(&s->dev[port]);
- }
+ switch (regnum) {
+ case AHCI_PORT_REG_LST_ADDR:
+ pr->lst_addr = val;
+ break;
+ case AHCI_PORT_REG_LST_ADDR_HI:
+ pr->lst_addr_hi = val;
+ break;
+ case AHCI_PORT_REG_FIS_ADDR:
+ pr->fis_addr = val;
+ break;
+ case AHCI_PORT_REG_FIS_ADDR_HI:
+ pr->fis_addr_hi = val;
+ break;
+ case AHCI_PORT_REG_IRQ_STAT:
+ pr->irq_stat &= ~val;
+ ahci_check_irq(s);
+ break;
+ case AHCI_PORT_REG_IRQ_MASK:
+ pr->irq_mask = val & 0xfdc000ff;
+ ahci_check_irq(s);
+ break;
+ case AHCI_PORT_REG_CMD:
+ /* Block any Read-only fields from being set;
+ * including LIST_ON and FIS_ON.
+ * The spec requires to set ICC bits to zero after the ICC change
+ * is done. We don't support ICC state changes, therefore always
+ * force the ICC bits to zero.
+ */
+ pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
+ (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK));
+
+ /* Check FIS RX and CLB engines */
+ ahci_cond_start_engines(&s->dev[port]);
+
+ /* XXX usually the FIS would be pending on the bus here and
+ issuing deferred until the OS enables FIS receival.
+ Instead, we only submit it once - which works in most
+ cases, but is a hack. */
+ if ((pr->cmd & PORT_CMD_FIS_ON) &&
+ !s->dev[port].init_d2h_sent) {
+ ahci_init_d2h(&s->dev[port]);
+ }
- check_cmd(s, port);
- break;
- case PORT_TFDATA:
- /* Read Only. */
- break;
- case PORT_SIG:
- /* Read Only */
- break;
- case PORT_SCR_STAT:
- /* Read Only */
- break;
- case PORT_SCR_CTL:
- if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
- ((val & AHCI_SCR_SCTL_DET) == 0)) {
- ahci_reset_port(s, port);
- }
- pr->scr_ctl = val;
- break;
- case PORT_SCR_ERR:
- pr->scr_err &= ~val;
- break;
- case PORT_SCR_ACT:
- /* RW1 */
- pr->scr_act |= val;
- break;
- case PORT_CMD_ISSUE:
- pr->cmd_issue |= val;
- check_cmd(s, port);
- break;
- default:
- break;
+ check_cmd(s, port);
+ break;
+ case AHCI_PORT_REG_TFDATA:
+ case AHCI_PORT_REG_SIG:
+ case AHCI_PORT_REG_SCR_STAT:
+ /* Read Only */
+ break;
+ case AHCI_PORT_REG_SCR_CTL:
+ if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
+ ((val & AHCI_SCR_SCTL_DET) == 0)) {
+ ahci_reset_port(s, port);
+ }
+ pr->scr_ctl = val;
+ break;
+ case AHCI_PORT_REG_SCR_ERR:
+ pr->scr_err &= ~val;
+ break;
+ case AHCI_PORT_REG_SCR_ACT:
+ /* RW1 */
+ pr->scr_act |= val;
+ break;
+ case AHCI_PORT_REG_CMD_ISSUE:
+ pr->cmd_issue |= val;
+ check_cmd(s, port);
+ break;
+ default:
+ trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum],
+ offset, val);
+ qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
+ "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32,
+ port, AHCIPortReg_lookup[regnum], offset, val);
+ break;
}
}
uint32_t val = 0;
if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
- switch (addr) {
- case HOST_CAP:
+ enum AHCIHostReg regnum = addr / 4;
+ assert(regnum < AHCI_HOST_REG__COUNT);
+
+ switch (regnum) {
+ case AHCI_HOST_REG_CAP:
val = s->control_regs.cap;
break;
- case HOST_CTL:
+ case AHCI_HOST_REG_CTL:
val = s->control_regs.ghc;
break;
- case HOST_IRQ_STAT:
+ case AHCI_HOST_REG_IRQ_STAT:
val = s->control_regs.irqstatus;
break;
- case HOST_PORTS_IMPL:
+ case AHCI_HOST_REG_PORTS_IMPL:
val = s->control_regs.impl;
break;
- case HOST_VERSION:
+ case AHCI_HOST_REG_VERSION:
val = s->control_regs.version;
break;
+ default:
+ trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum],
+ addr);
}
-
- DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
+ trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val);
} else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
(addr < (AHCI_PORT_REGS_START_ADDR +
(s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
addr & AHCI_PORT_ADDR_OFFSET_MASK);
+ } else {
+ trace_ahci_mem_read_32_default(s, addr, val);
}
+ trace_ahci_mem_read_32(s, addr, val);
return val;
}
if (ofst + size <= 4) {
val = lo >> (ofst * 8);
} else {
- g_assert_cmpint(size, >, 1);
+ g_assert(size > 1);
/* If the 64bit read is unaligned, we will produce undefined
* results. AHCI does not support unaligned 64bit reads. */
val = (hi << 32 | lo) >> (ofst * 8);
}
- DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
- addr, val, size);
+ trace_ahci_mem_read(opaque, size, addr, val);
return val;
}
{
AHCIState *s = opaque;
- DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
- addr, val, size);
+ trace_ahci_mem_write(s, size, addr, val);
/* Only aligned reads are allowed on AHCI */
if (addr & 3) {
}
if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
- DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val);
+ enum AHCIHostReg regnum = addr / 4;
+ assert(regnum < AHCI_HOST_REG__COUNT);
- switch (addr) {
- case HOST_CAP: /* R/WO, RO */
- /* FIXME handle R/WO */
- break;
- case HOST_CTL: /* R/W */
- if (val & HOST_CTL_RESET) {
- DPRINTF(-1, "HBA Reset\n");
- ahci_reset(s);
- } else {
- s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
- ahci_check_irq(s);
- }
- break;
- case HOST_IRQ_STAT: /* R/WC, RO */
- s->control_regs.irqstatus &= ~val;
+ switch (regnum) {
+ case AHCI_HOST_REG_CAP: /* R/WO, RO */
+ /* FIXME handle R/WO */
+ break;
+ case AHCI_HOST_REG_CTL: /* R/W */
+ if (val & HOST_CTL_RESET) {
+ ahci_reset(s);
+ } else {
+ s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
ahci_check_irq(s);
- break;
- case HOST_PORTS_IMPL: /* R/WO, RO */
- /* FIXME handle R/WO */
- break;
- case HOST_VERSION: /* RO */
- /* FIXME report write? */
- break;
- default:
- DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr);
+ }
+ break;
+ case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */
+ s->control_regs.irqstatus &= ~val;
+ ahci_check_irq(s);
+ break;
+ case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */
+ /* FIXME handle R/WO */
+ break;
+ case AHCI_HOST_REG_VERSION: /* RO */
+ /* FIXME report write? */
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "Attempted write to unimplemented register: "
+ "AHCI host register %s, "
+ "offset 0x%"PRIx64": 0x%"PRIx64,
+ AHCIHostReg_lookup[regnum], addr, val);
+ trace_ahci_mem_write_host_unimpl(s, size,
+ AHCIHostReg_lookup[regnum], addr);
}
+ trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum],
+ addr, val);
} else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
(addr < (AHCI_PORT_REGS_START_ADDR +
- (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
+ (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
+ } else {
+ qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
+ "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64,
+ addr, val);
+ trace_ahci_mem_write_unimpl(s, size, addr, val);
}
-
}
static const MemoryRegionOps ahci_mem_ops = {
qemu_bh_delete(ad->check_bh);
ad->check_bh = NULL;
- if ((ad->busy_slot != -1) &&
- !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) {
- /* no longer busy */
- ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
- ad->busy_slot = -1;
- }
-
check_cmd(ad->hba, ad->port_no);
}
s->sector = sig >> 8 & 0xFF;
s->nsector = sig & 0xFF;
- DPRINTF(ad->port_no, "set hcyl:lcyl:sect:nsect = 0x%08x\n", sig);
+ trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector,
+ s->lcyl, s->hcyl, sig);
}
static void ahci_reset_port(AHCIState *s, int port)
IDEState *ide_state = &d->port.ifs[0];
int i;
- DPRINTF(port, "reset port\n");
+ trace_ahci_reset_port(s, port);
ide_bus_reset(&d->port);
ide_state->ncq_queues = AHCI_MAX_CMDS;
ahci_init_d2h(d);
}
-static void debug_print_fis(uint8_t *fis, int cmd_len)
+/* Buffer pretty output based on a raw FIS structure. */
+static char *ahci_pretty_buffer_fis(uint8_t *fis, int cmd_len)
{
-#if DEBUG_AHCI
int i;
+ GString *s = g_string_new("FIS:");
- fprintf(stderr, "fis:");
for (i = 0; i < cmd_len; i++) {
if ((i & 0xf) == 0) {
- fprintf(stderr, "\n%02x:",i);
+ g_string_append_printf(s, "\n0x%02x: ", i);
}
- fprintf(stderr, "%02x ",fis[i]);
+ g_string_append_printf(s, "%02x ", fis[i]);
}
- fprintf(stderr, "\n");
-#endif
+ g_string_append_c(s, '\n');
+
+ return g_string_free(s, FALSE);
}
static bool ahci_map_fis_address(AHCIDevice *ad)
static void ahci_unmap_fis_address(AHCIDevice *ad)
{
if (ad->res_fis == NULL) {
- DPRINTF(ad->port_no, "Attempt to unmap NULL FIS address\n");
+ trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no);
return;
}
ad->port_regs.cmd &= ~PORT_CMD_FIS_ON;
static void ahci_unmap_clb_address(AHCIDevice *ad)
{
if (ad->lst == NULL) {
- DPRINTF(ad->port_no, "Attempt to unmap NULL CLB address\n");
+ trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no);
return;
}
ad->port_regs.cmd &= ~PORT_CMD_LIST_ON;
/* Trigger IRQ if interrupt bit is set (which currently, it always is) */
if (sdb_fis->flags & 0x40) {
- ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);
+ ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);
}
}
-static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)
+static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i)
{
AHCIPortRegs *pr = &ad->port_regs;
uint8_t *pio_fis;
pio_fis = &ad->res_fis[RES_FIS_PSFIS];
pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP;
- pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
+ pio_fis[1] = (pio_fis_i ? (1 << 6) : 0);
pio_fis[2] = s->status;
pio_fis[3] = s->error;
ad->port.ifs[0].status;
if (pio_fis[2] & ERR_STAT) {
- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
}
-
- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);
}
static bool ahci_write_fis_d2h(AHCIDevice *ad)
d2h_fis = &ad->res_fis[RES_FIS_RFIS];
d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H;
- d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
+ d2h_fis[1] = (1 << 6); /* interrupt bit */
d2h_fis[2] = s->status;
d2h_fis[3] = s->error;
ad->port.ifs[0].status;
if (d2h_fis[2] & ERR_STAT) {
- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
}
- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);
+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);
return true;
}
IDEBus *bus = &ad->port;
BusState *qbus = BUS(bus);
+ trace_ahci_populate_sglist(ad->hba, ad->port_no);
+
if (!prdtl) {
- DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);
+ trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts);
return -1;
}
/* map PRDT */
if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,
DMA_DIRECTION_TO_DEVICE))){
- DPRINTF(ad->port_no, "map failed\n");
+ trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no);
return -1;
}
if (prdt_len < real_prdt_len) {
- DPRINTF(ad->port_no, "mapped less than expected\n");
+ trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no);
r = -1;
goto out;
}
sum += tbl_entry_size;
}
if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {
- DPRINTF(ad->port_no, "%s: Incorrect offset! "
- "off_idx: %d, off_pos: %"PRId64"\n",
- __func__, off_idx, off_pos);
+ trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no,
+ off_idx, off_pos);
r = -1;
goto out;
}
ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs);
- DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n",
- ncq_tfs->tag);
+ trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
+ ncq_tfs->tag);
block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk),
&ncq_tfs->acct);
switch (ncq_tfs->cmd) {
case READ_FPDMA_QUEUED:
- DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", tag %d\n",
- ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag);
-
- DPRINTF(port, "tag %d aio read %"PRId64"\n",
- ncq_tfs->tag, ncq_tfs->lba);
-
+ trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
+ ncq_tfs->sector_count, ncq_tfs->lba);
dma_acct_start(ide_state->blk, &ncq_tfs->acct,
&ncq_tfs->sglist, BLOCK_ACCT_READ);
ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist,
ncq_cb, ncq_tfs);
break;
case WRITE_FPDMA_QUEUED:
- DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n",
- ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag);
-
- DPRINTF(port, "tag %d aio write %"PRId64"\n",
- ncq_tfs->tag, ncq_tfs->lba);
-
+ trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
+ ncq_tfs->sector_count, ncq_tfs->lba);
dma_acct_start(ide_state->blk, &ncq_tfs->acct,
&ncq_tfs->sglist, BLOCK_ACCT_WRITE);
ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,
ncq_cb, ncq_tfs);
break;
default:
- DPRINTF(port, "error: unsupported NCQ command (0x%02x) received\n",
- ncq_tfs->cmd);
+ trace_execute_ncq_command_unsup(ad->hba, port,
+ ncq_tfs->tag, ncq_tfs->cmd);
ncq_err(ncq_tfs);
}
}
uint8_t slot)
{
AHCIDevice *ad = &s->dev[port];
- IDEState *ide_state = &ad->port.ifs[0];
NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;
uint8_t tag = ncq_fis->tag >> 3;
NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag];
g_assert(is_ncq(ncq_fis->command));
if (ncq_tfs->used) {
/* error - already in use */
- fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag);
+ fprintf(stderr, "%s: tag %d already used\n", __func__, tag);
return;
}
/* Sanity-check the NCQ packet */
if (tag != slot) {
- DPRINTF(port, "Warn: NCQ slot (%d) did not match the given tag (%d)\n",
- slot, tag);
+ trace_process_ncq_command_mismatch(s, port, tag, slot);
}
if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) {
- DPRINTF(port, "Warn: Attempt to use NCQ auxiliary fields.\n");
+ trace_process_ncq_command_aux(s, port, tag);
}
if (ncq_fis->prio || ncq_fis->icc) {
- DPRINTF(port, "Warn: Unsupported attempt to use PRIO/ICC fields\n");
+ trace_process_ncq_command_prioicc(s, port, tag);
}
if (ncq_fis->fua & NCQ_FIS_FUA_MASK) {
- DPRINTF(port, "Warn: Unsupported attempt to use Force Unit Access\n");
+ trace_process_ncq_command_fua(s, port, tag);
}
if (ncq_fis->tag & NCQ_FIS_RARC_MASK) {
- DPRINTF(port, "Warn: Unsupported attempt to use Rebuild Assist\n");
+ trace_process_ncq_command_rarc(s, port, tag);
}
ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) |
"is smaller than the requested size (0x%zx)",
ncq_tfs->sglist.size, size);
ncq_err(ncq_tfs);
- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW);
+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);
return;
} else if (ncq_tfs->sglist.size != size) {
- DPRINTF(port, "Warn: PRDTL (0x%zx)"
- " does not match requested size (0x%zx)",
- ncq_tfs->sglist.size, size);
+ trace_process_ncq_command_large(s, port, tag,
+ ncq_tfs->sglist.size, size);
}
- DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", "
- "drive max %"PRId64"\n",
- ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 1,
- ide_state->nb_sectors - 1);
-
+ trace_process_ncq_command(s, port, tag,
+ ncq_fis->command,
+ ncq_tfs->lba,
+ ncq_tfs->lba + ncq_tfs->sector_count - 1);
execute_ncq_command(ncq_tfs);
}
uint16_t opts = le16_to_cpu(cmd->opts);
if (cmd_fis[1] & 0x0F) {
- DPRINTF(port, "Port Multiplier not supported."
- " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
- cmd_fis[0], cmd_fis[1], cmd_fis[2]);
+ trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1],
+ cmd_fis[2], cmd_fis[3]);
return;
}
if (cmd_fis[1] & 0x70) {
- DPRINTF(port, "Reserved flags set in H2D Register FIS."
- " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
- cmd_fis[0], cmd_fis[1], cmd_fis[2]);
+ trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1],
+ cmd_fis[2], cmd_fis[3]);
return;
}
* table to ide_state->io_buffer */
if (opts & AHCI_CMD_ATAPI) {
memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
- debug_print_fis(ide_state->io_buffer, 0x10);
- s->dev[port].done_atapi_packet = false;
- /* XXX send PIO setup FIS */
+ if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) {
+ char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10);
+ trace_handle_reg_h2d_fis_dump(s, port, pretty_fis);
+ g_free(pretty_fis);
+ }
}
ide_state->error = 0;
-
+ s->dev[port].done_first_drq = false;
/* Reset transferred byte counter */
cmd->status = 0;
if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
/* Engine currently busy, try again later */
- DPRINTF(port, "engine busy\n");
+ trace_handle_cmd_busy(s, port);
return -1;
}
if (!s->dev[port].lst) {
- DPRINTF(port, "error: lst not given but cmd handled");
+ trace_handle_cmd_nolist(s, port);
return -1;
}
cmd = get_cmd_header(s, port, slot);
/* The device we are working for */
ide_state = &s->dev[port].port.ifs[0];
if (!ide_state->blk) {
- DPRINTF(port, "error: guest accessed unused port");
+ trace_handle_cmd_badport(s, port);
return -1;
}
cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,
DMA_DIRECTION_FROM_DEVICE);
if (!cmd_fis) {
- DPRINTF(port, "error: guest passed us an invalid cmd fis\n");
+ trace_handle_cmd_badfis(s, port);
return -1;
} else if (cmd_len != 0x80) {
- ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR);
- DPRINTF(port, "error: dma_memory_map failed: "
- "(len(%02"PRIx64") != 0x80)\n",
- cmd_len);
+ ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS);
+ trace_handle_cmd_badmap(s, port, cmd_len);
goto out;
}
- debug_print_fis(cmd_fis, 0x80);
-
+ if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) {
+ char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80);
+ trace_handle_cmd_fis_dump(s, port, pretty_fis);
+ g_free(pretty_fis);
+ }
switch (cmd_fis[0]) {
case SATA_FIS_TYPE_REGISTER_H2D:
handle_reg_h2d_fis(s, port, slot, cmd_fis);
break;
default:
- DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
- "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
- cmd_fis[2]);
+ trace_handle_cmd_unhandled_fis(s, port,
+ cmd_fis[0], cmd_fis[1], cmd_fis[2]);
break;
}
return 0;
}
-/* DMA dev <-> ram */
-static void ahci_start_transfer(IDEDMA *dma)
+/* Transfer PIO data between RAM and device */
+static void ahci_pio_transfer(IDEDMA *dma)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
IDEState *s = &ad->port.ifs[0];
int is_write = opts & AHCI_CMD_WRITE;
int is_atapi = opts & AHCI_CMD_ATAPI;
int has_sglist = 0;
+ bool pio_fis_i;
+
+ /* The PIO Setup FIS is received prior to transfer, but the interrupt
+ * is only triggered after data is received.
+ *
+ * The device only sets the 'I' bit in the PIO Setup FIS for device->host
+ * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after
+ * the first (see "DPIOO1"). The latter is consistent with the spec's
+ * description of the PACKET protocol, where the command part of ATAPI requests
+ * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests
+ * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs.
+ */
+ pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write);
+ ahci_write_fis_pio(ad, size, pio_fis_i);
- if (is_atapi && !ad->done_atapi_packet) {
+ if (is_atapi && !ad->done_first_drq) {
/* already prepopulated iobuffer */
- ad->done_atapi_packet = true;
- size = 0;
goto out;
}
has_sglist = 1;
}
- DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n",
- is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata",
- has_sglist ? "" : "o");
+ trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read",
+ size, is_atapi ? "atapi" : "ata",
+ has_sglist ? "" : "o");
if (has_sglist && size) {
if (is_write) {
}
}
-out:
- /* declare that we processed everything */
- s->data_ptr = s->data_end;
-
/* Update number of transferred bytes, destroy sglist */
dma_buf_commit(s, size);
- s->end_transfer_func(s);
+out:
+ /* declare that we processed everything */
+ s->data_ptr = s->data_end;
- if (!(s->status & DRQ_STAT)) {
- /* done with PIO send/receive */
- ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status));
+ ad->done_first_drq = true;
+ if (pio_fis_i) {
+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
}
}
BlockCompletionFunc *dma_cb)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
- DPRINTF(ad->port_no, "\n");
+ trace_ahci_start_dma(ad->hba, ad->port_no);
s->io_buffer_offset = 0;
dma_cb(s, 0);
}
if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd,
limit, s->io_buffer_offset) == -1) {
- DPRINTF(ad->port_no, "ahci_dma_prepare_buf failed.\n");
+ trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no);
return -1;
}
s->io_buffer_size = s->sg.size;
- DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size);
+ trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size);
return s->io_buffer_size;
}
/* free sglist, update byte count */
dma_buf_commit(s, l);
-
s->io_buffer_index += l;
- DPRINTF(ad->port_no, "len=%#x\n", l);
-
+ trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l);
return 1;
}
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
- DPRINTF(ad->port_no, "cmd done\n");
+ trace_ahci_cmd_done(ad->hba, ad->port_no);
+
+ /* no longer busy */
+ if (ad->busy_slot != -1) {
+ ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
+ ad->busy_slot = -1;
+ }
/* update d2h status */
ahci_write_fis_d2h(ad);
- if (!ad->check_bh) {
- /* maybe we still have something to process, check later */
+ if (ad->port_regs.cmd_issue && !ad->check_bh) {
ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad);
qemu_bh_schedule(ad->check_bh);
}
.start_dma = ahci_start_dma,
.restart = ahci_restart,
.restart_dma = ahci_restart_dma,
- .start_transfer = ahci_start_transfer,
+ .pio_transfer = ahci_pio_transfer,
.prepare_buf = ahci_dma_prepare_buf,
.commit_buf = ahci_commit_buf,
.rw_buf = ahci_dma_rw_buf,
ide_exit(s);
}
+ object_unparent(OBJECT(&ad->port));
}
g_free(s->dev);
AHCIPortRegs *pr;
int i;
+ trace_ahci_reset(s);
+
s->control_regs.irqstatus = 0;
/* AHCI Enable (AE)
* The implementation of this bit is dependent upon the value of the
VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
- VMSTATE_BOOL(done_atapi_packet, AHCIDevice),
+ VMSTATE_BOOL(done_first_drq, AHCIDevice),
VMSTATE_INT32(busy_slot, AHCIDevice),
VMSTATE_BOOL(init_d2h_sent, AHCIDevice),
VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS,
.class_init = sysbus_ahci_class_init,
};
-#define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_BISTSR ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_BISTDECR ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_DIAGNR0 ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_DIAGNR1 ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_OOBR ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_PHYCS0R ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_PHYCS1R ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_PHYCS2R ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_TIMER1MS ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_GPARAM1R ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_GPARAM2R ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_PPARAMR ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_TESTR ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_VERSIONR ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_IDR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
-#define ALLWINNER_AHCI_RWCR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
-
-static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,
- unsigned size)
-{
- AllwinnerAHCIState *a = opaque;
- uint64_t val = a->regs[addr/4];
-
- switch (addr / 4) {
- case ALLWINNER_AHCI_PHYCS0R:
- val |= 0x2 << 28;
- break;
- case ALLWINNER_AHCI_PHYCS2R:
- val &= ~(0x1 << 24);
- break;
- }
- DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
- addr, val, size);
- return val;
-}
-
-static void allwinner_ahci_mem_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
-{
- AllwinnerAHCIState *a = opaque;
-
- DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
- addr, val, size);
- a->regs[addr/4] = val;
-}
-
-static const MemoryRegionOps allwinner_ahci_mem_ops = {
- .read = allwinner_ahci_mem_read,
- .write = allwinner_ahci_mem_write,
- .valid.min_access_size = 4,
- .valid.max_access_size = 4,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
-static void allwinner_ahci_init(Object *obj)
-{
- SysbusAHCIState *s = SYSBUS_AHCI(obj);
- AllwinnerAHCIState *a = ALLWINNER_AHCI(obj);
-
- memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a,
- "allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE);
- memory_region_add_subregion(&s->ahci.mem, ALLWINNER_AHCI_MMIO_OFF,
- &a->mmio);
-}
-
-static const VMStateDescription vmstate_allwinner_ahci = {
- .name = "allwinner-ahci",
- .version_id = 1,
- .minimum_version_id = 1,
- .fields = (VMStateField[]) {
- VMSTATE_UINT32_ARRAY(regs, AllwinnerAHCIState,
- ALLWINNER_AHCI_MMIO_SIZE/4),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static void allwinner_ahci_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- dc->vmsd = &vmstate_allwinner_ahci;
-}
-
-static const TypeInfo allwinner_ahci_info = {
- .name = TYPE_ALLWINNER_AHCI,
- .parent = TYPE_SYSBUS_AHCI,
- .instance_size = sizeof(AllwinnerAHCIState),
- .instance_init = allwinner_ahci_init,
- .class_init = allwinner_ahci_class_init,
-};
-
static void sysbus_ahci_register_types(void)
{
type_register_static(&sysbus_ahci_info);
- type_register_static(&allwinner_ahci_info);
}
type_init(sysbus_ahci_register_types)
projects / qemu.git / blobdiff