ac97: Use PCI DMA stub functions

[qemu.git] / hw / apic.c

diff --git a/hw/apic.c b/hw/apic.c
index 626f72fd0e80cf11604a769b70f4161eb573ab1a..8289eef5b83df249a9d7b049e4878b2761f28c81 100644 (file)
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -14,16 +14,16 @@
  * Lesser General Public License for more details.
  *
  * You should have received a copy of the GNU Lesser General Public
  * Lesser General Public License for more details.
  *
  * You should have received a copy of the GNU Lesser General Public

- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>

  */
 #include "hw.h"
  */
 #include "hw.h"

-#include "pc.h"
+#include "apic.h"
+#include "ioapic.h"

 #include "qemu-timer.h"
 #include "host-utils.h"
 #include "qemu-timer.h"
 #include "host-utils.h"

-
-//#define DEBUG_APIC
-//#define DEBUG_IOAPIC
+#include "sysbus.h"
+#include "trace.h"
+#include "pc.h"

 
 /* APIC Local Vector Table */
 #define APIC_LVT_TIMER   0
 
 /* APIC Local Vector Table */
 #define APIC_LVT_TIMER   0


@@ -57,17 +57,32 @@
 #define        APIC_INPUT_POLARITY             (1<<13)
 #define        APIC_SEND_PENDING               (1<<12)
 
 #define        APIC_INPUT_POLARITY             (1<<13)
 #define        APIC_SEND_PENDING               (1<<12)
 

-#define IOAPIC_NUM_PINS                        0x18
-

 #define ESR_ILLEGAL_ADDRESS (1 << 7)
 
 #define ESR_ILLEGAL_ADDRESS (1 << 7)
 

-#define APIC_SV_ENABLE (1 << 8)
+#define APIC_SV_DIRECTED_IO             (1<<12)
+#define APIC_SV_ENABLE                  (1<<8)

 
 #define MAX_APICS 255
 #define MAX_APIC_WORDS 8
 
 
 #define MAX_APICS 255
 #define MAX_APIC_WORDS 8
 

-typedef struct APICState {
-    CPUState *cpu_env;
+/* Intel APIC constants: from include/asm/msidef.h */
+#define MSI_DATA_VECTOR_SHIFT          0
+#define MSI_DATA_VECTOR_MASK           0x000000ff
+#define MSI_DATA_DELIVERY_MODE_SHIFT   8
+#define MSI_DATA_TRIGGER_SHIFT         15
+#define MSI_DATA_LEVEL_SHIFT           14
+#define MSI_ADDR_DEST_MODE_SHIFT       2
+#define MSI_ADDR_DEST_ID_SHIFT         12
+#define        MSI_ADDR_DEST_ID_MASK           0x00ffff0
+
+#define MSI_ADDR_SIZE                   0x100000
+
+typedef struct APICState APICState;
+
+struct APICState {
+    SysBusDevice busdev;
+    MemoryRegion io_memory;
+    void *cpu_env;

     uint32_t apicbase;
     uint8_t id;
     uint8_t arb_id;
     uint32_t apicbase;
     uint8_t id;
     uint8_t arb_id;


@@ -86,24 +101,25 @@ typedef struct APICState {
     int count_shift;
     uint32_t initial_count;
     int64_t initial_count_load_time, next_time;
     int count_shift;
     uint32_t initial_count;
     int64_t initial_count_load_time, next_time;

+    uint32_t idx;

     QEMUTimer *timer;
     QEMUTimer *timer;

-} APICState;
-
-struct IOAPICState {
-    uint8_t id;
-    uint8_t ioregsel;
-
-    uint32_t irr;
-    uint64_t ioredtbl[IOAPIC_NUM_PINS];
+    int sipi_vector;
+    int wait_for_sipi;

 };
 
 };
 

-static int apic_io_memory;

 static APICState *local_apics[MAX_APICS + 1];
 static APICState *local_apics[MAX_APICS + 1];

-static int last_apic_id = 0;
+static int apic_irq_delivered;

 
 

-static void apic_init_ipi(APICState *s);

 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 static void apic_update_irq(APICState *s);
 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 static void apic_update_irq(APICState *s);

+static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
+                                      uint8_t dest, uint8_t dest_mode);
+
+/* Find first bit starting from msb */
+static int fls_bit(uint32_t value)
+{
+    return 31 - clz32(value);
+}

 
 /* Find first bit starting from lsb */
 static int ffs_bit(uint32_t value)
 
 /* Find first bit starting from lsb */
 static int ffs_bit(uint32_t value)


@@ -127,26 +143,35 @@ static inline void reset_bit(uint32_t *tab, int index)
     tab[i] &= ~mask;
 }
 
     tab[i] &= ~mask;
 }
 

-static void apic_local_deliver(CPUState *env, int vector)
+static inline int get_bit(uint32_t *tab, int index)
+{
+    int i, mask;
+    i = index >> 5;
+    mask = 1 << (index & 0x1f);
+    return !!(tab[i] & mask);
+}
+
+static void apic_local_deliver(APICState *s, int vector)

 {
 {

-    APICState *s = env->apic_state;

     uint32_t lvt = s->lvt[vector];
     int trigger_mode;
 
     uint32_t lvt = s->lvt[vector];
     int trigger_mode;
 

+    trace_apic_local_deliver(vector, (lvt >> 8) & 7);
+

     if (lvt & APIC_LVT_MASKED)
         return;
 
     switch ((lvt >> 8) & 7) {
     case APIC_DM_SMI:
     if (lvt & APIC_LVT_MASKED)
         return;
 
     switch ((lvt >> 8) & 7) {
     case APIC_DM_SMI:

-        cpu_interrupt(env, CPU_INTERRUPT_SMI);
+        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);

         break;
 
     case APIC_DM_NMI:
         break;
 
     case APIC_DM_NMI:

-        cpu_interrupt(env, CPU_INTERRUPT_NMI);
+        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);

         break;
 
     case APIC_DM_EXTINT:
         break;
 
     case APIC_DM_EXTINT:

-        cpu_interrupt(env, CPU_INTERRUPT_HARD);
+        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);

         break;
 
     case APIC_DM_FIXED:
         break;
 
     case APIC_DM_FIXED:


@@ -158,12 +183,13 @@ static void apic_local_deliver(CPUState *env, int vector)
     }
 }
 
     }
 }
 

-void apic_deliver_pic_intr(CPUState *env, int level)
+void apic_deliver_pic_intr(DeviceState *d, int level)

 {
 {

-    if (level)
-        apic_local_deliver(env, APIC_LVT_LINT0);
-    else {
-        APICState *s = env->apic_state;
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
+
+    if (level) {
+        apic_local_deliver(s, APIC_LVT_LINT0);
+    } else {

         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 
         switch ((lvt >> 8) & 7) {
         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 
         switch ((lvt >> 8) & 7) {


@@ -173,7 +199,7 @@ void apic_deliver_pic_intr(CPUState *env, int level)
             reset_bit(s->irr, lvt & 0xff);
             /* fall through */
         case APIC_DM_EXTINT:
             reset_bit(s->irr, lvt & 0xff);
             /* fall through */
         case APIC_DM_EXTINT:

-            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+            cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);

             break;
         }
     }
             break;
         }
     }


@@ -198,8 +224,7 @@ void apic_deliver_pic_intr(CPUState *env, int level)
 }
 
 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 }
 
 static void apic_bus_deliver(const uint32_t *deliver_bitmask,

-                             uint8_t delivery_mode,
-                             uint8_t vector_num, uint8_t polarity,
+                             uint8_t delivery_mode, uint8_t vector_num,

                              uint8_t trigger_mode)
 {
     APICState *apic_iter;
                              uint8_t trigger_mode)
 {
     APICState *apic_iter;


@@ -241,7 +266,7 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
         case APIC_DM_INIT:
             /* normal INIT IPI sent to processors */
             foreach_apic(apic_iter, deliver_bitmask,
         case APIC_DM_INIT:
             /* normal INIT IPI sent to processors */
             foreach_apic(apic_iter, deliver_bitmask,

-                         apic_init_ipi(apic_iter) );
+                         cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );

             return;
 
         case APIC_DM_EXTINT:
             return;
 
         case APIC_DM_EXTINT:


@@ -256,42 +281,60 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 }
 
                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 }
 

-void cpu_set_apic_base(CPUState *env, uint64_t val)
+void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
+                      uint8_t vector_num, uint8_t trigger_mode)

 {
 {

-    APICState *s = env->apic_state;
-#ifdef DEBUG_APIC
-    printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
-#endif
+    uint32_t deliver_bitmask[MAX_APIC_WORDS];
+
+    trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
+                           trigger_mode);
+
+    apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
+    apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
+}
+
+void cpu_set_apic_base(DeviceState *d, uint64_t val)
+{
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
+
+    trace_cpu_set_apic_base(val);
+
+    if (!s)
+        return;

     s->apicbase = (val & 0xfffff000) |
         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
     /* if disabled, cannot be enabled again */
     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
     s->apicbase = (val & 0xfffff000) |
         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
     /* if disabled, cannot be enabled again */
     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;

-        env->cpuid_features &= ~CPUID_APIC;
+        cpu_clear_apic_feature(s->cpu_env);

         s->spurious_vec &= ~APIC_SV_ENABLE;
     }
 }
 
         s->spurious_vec &= ~APIC_SV_ENABLE;
     }
 }
 

-uint64_t cpu_get_apic_base(CPUState *env)
+uint64_t cpu_get_apic_base(DeviceState *d)

 {
 {

-    APICState *s = env->apic_state;
-#ifdef DEBUG_APIC
-    printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
-#endif
-    return s->apicbase;
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
+
+    trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
+
+    return s ? s->apicbase : 0;

 }
 
 }
 

-void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
+void cpu_set_apic_tpr(DeviceState *d, uint8_t val)

 {
 {

-    APICState *s = env->apic_state;
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
+
+    if (!s)
+        return;

     s->tpr = (val & 0x0f) << 4;
     apic_update_irq(s);
 }
 
     s->tpr = (val & 0x0f) << 4;
     apic_update_irq(s);
 }
 

-uint8_t cpu_get_apic_tpr(CPUX86State *env)
+uint8_t cpu_get_apic_tpr(DeviceState *d)

 {
 {

-    APICState *s = env->apic_state;
-    return s->tpr >> 4;
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
+
+    return s ? s->tpr >> 4 : 0;

 }
 
 /* return -1 if no bit is set */
 }
 
 /* return -1 if no bit is set */


@@ -300,7 +343,7 @@ static int get_highest_priority_int(uint32_t *tab)
     int i;
     for(i = 7; i >= 0; i--) {
         if (tab[i] != 0) {
     int i;
     for(i = 7; i >= 0; i--) {
         if (tab[i] != 0) {

-            return i * 32 + fls(tab[i]);
+            return i * 32 + fls_bit(tab[i]);

         }
     }
     return -1;
         }
     }
     return -1;


@@ -328,23 +371,61 @@ static int apic_get_arb_pri(APICState *s)
     return 0;
 }
 
     return 0;
 }
 

-/* signal the CPU if an irq is pending */
-static void apic_update_irq(APICState *s)
+
+/*
+ * <0 - low prio interrupt,
+ * 0  - no interrupt,
+ * >0 - interrupt number
+ */
+static int apic_irq_pending(APICState *s)

 {
     int irrv, ppr;
 {
     int irrv, ppr;

-    if (!(s->spurious_vec & APIC_SV_ENABLE))
-        return;

     irrv = get_highest_priority_int(s->irr);
     irrv = get_highest_priority_int(s->irr);

-    if (irrv < 0)
-        return;
+    if (irrv < 0) {
+        return 0;
+    }

     ppr = apic_get_ppr(s);
     ppr = apic_get_ppr(s);

-    if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
+    if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
+        return -1;
+    }
+
+    return irrv;
+}
+
+/* signal the CPU if an irq is pending */
+static void apic_update_irq(APICState *s)
+{
+    if (!(s->spurious_vec & APIC_SV_ENABLE)) {

         return;
         return;

-    cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
+    }
+    if (apic_irq_pending(s) > 0) {
+        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
+    } else if (apic_accept_pic_intr(&s->busdev.qdev) &&
+               pic_get_output(isa_pic)) {
+        apic_deliver_pic_intr(&s->busdev.qdev, 1);
+    }
+}
+
+void apic_reset_irq_delivered(void)
+{
+    trace_apic_reset_irq_delivered(apic_irq_delivered);
+
+    apic_irq_delivered = 0;
+}
+
+int apic_get_irq_delivered(void)
+{
+    trace_apic_get_irq_delivered(apic_irq_delivered);
+
+    return apic_irq_delivered;

 }
 
 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 {
 }
 
 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 {

+    apic_irq_delivered += !get_bit(s->irr, vector_num);
+
+    trace_apic_set_irq(apic_irq_delivered);
+

     set_bit(s->irr, vector_num);
     if (trigger_mode)
         set_bit(s->tmr, vector_num);
     set_bit(s->irr, vector_num);
     if (trigger_mode)
         set_bit(s->tmr, vector_num);


@@ -360,11 +441,31 @@ static void apic_eoi(APICState *s)
     if (isrv < 0)
         return;
     reset_bit(s->isr, isrv);
     if (isrv < 0)
         return;
     reset_bit(s->isr, isrv);

-    /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
-            set the remote IRR bit for level triggered interrupts. */
+    if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
+        ioapic_eoi_broadcast(isrv);
+    }

     apic_update_irq(s);
 }
 
     apic_update_irq(s);
 }
 

+static int apic_find_dest(uint8_t dest)
+{
+    APICState *apic = local_apics[dest];
+    int i;
+
+    if (apic && apic->id == dest)
+        return dest;  /* shortcut in case apic->id == apic->idx */
+
+    for (i = 0; i < MAX_APICS; i++) {
+        apic = local_apics[i];
+       if (apic && apic->id == dest)
+            return i;
+        if (!apic)
+            break;
+    }
+
+    return -1;
+}
+

 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
                                       uint8_t dest, uint8_t dest_mode)
 {
 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
                                       uint8_t dest, uint8_t dest_mode)
 {


@@ -375,8 +476,10 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
         if (dest == 0xff) {
             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
         } else {
         if (dest == 0xff) {
             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
         } else {

+            int idx = apic_find_dest(dest);

             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));

-            set_bit(deliver_bitmask, dest);
+            if (idx >= 0)
+                set_bit(deliver_bitmask, idx);

         }
     } else {
         /* XXX: cluster mode */
         }
     } else {
         /* XXX: cluster mode */


@@ -393,16 +496,21 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
                         set_bit(deliver_bitmask, i);
                     }
                 }
                         set_bit(deliver_bitmask, i);
                     }
                 }

+            } else {
+                break;

             }
         }
     }
 }
 
             }
         }
     }
 }
 

-
-static void apic_init_ipi(APICState *s)
+void apic_init_reset(DeviceState *d)

 {
 {

+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);

     int i;
 
     int i;
 

+    if (!s)
+        return;
+

     s->tpr = 0;
     s->spurious_vec = 0xff;
     s->log_dest = 0;
     s->tpr = 0;
     s->spurious_vec = 0xff;
     s->log_dest = 0;


@@ -419,29 +527,32 @@ static void apic_init_ipi(APICState *s)
     s->initial_count = 0;
     s->initial_count_load_time = 0;
     s->next_time = 0;
     s->initial_count = 0;
     s->initial_count_load_time = 0;
     s->next_time = 0;

-
-    cpu_reset(s->cpu_env);
-
-    if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
-        s->cpu_env->halted = 1;
+    s->wait_for_sipi = 1;

 }
 
 }
 

-/* send a SIPI message to the CPU to start it */

 static void apic_startup(APICState *s, int vector_num)
 {
 static void apic_startup(APICState *s, int vector_num)
 {

-    CPUState *env = s->cpu_env;
-    if (!env->halted)
+    s->sipi_vector = vector_num;
+    cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
+}
+
+void apic_sipi(DeviceState *d)
+{
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
+
+    cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
+
+    if (!s->wait_for_sipi)

         return;
         return;

-    env->eip = 0;
-    cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
-                           0xffff, 0);
-    env->halted = 0;
+    cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
+    s->wait_for_sipi = 0;

 }
 
 }
 

-static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
+static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,

                          uint8_t delivery_mode, uint8_t vector_num,
                          uint8_t delivery_mode, uint8_t vector_num,

-                         uint8_t polarity, uint8_t trigger_mode)
+                         uint8_t trigger_mode)

 {
 {

+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);

     uint32_t deliver_bitmask[MAX_APIC_WORDS];
     int dest_shorthand = (s->icr[0] >> 18) & 3;
     APICState *apic_iter;
     uint32_t deliver_bitmask[MAX_APIC_WORDS];
     int dest_shorthand = (s->icr[0] >> 18) & 3;
     APICState *apic_iter;


@@ -452,14 +563,14 @@ static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
         break;
     case 1:
         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
         break;
     case 1:
         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));

-        set_bit(deliver_bitmask, s->id);
+        set_bit(deliver_bitmask, s->idx);

         break;
     case 2:
         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
         break;
     case 3:
         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
         break;
     case 2:
         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
         break;
     case 3:
         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));

-        reset_bit(deliver_bitmask, s->id);
+        reset_bit(deliver_bitmask, s->idx);

         break;
     }
 
         break;
     }
 


@@ -482,13 +593,12 @@ static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
             return;
     }
 
             return;
     }
 

-    apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
-                     trigger_mode);
+    apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);

 }
 
 }
 

-int apic_get_interrupt(CPUState *env)
+int apic_get_interrupt(DeviceState *d)

 {
 {

-    APICState *s = env->apic_state;
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);

     int intno;
 
     /* if the APIC is installed or enabled, we let the 8259 handle the
     int intno;
 
     /* if the APIC is installed or enabled, we let the 8259 handle the


@@ -498,21 +608,22 @@ int apic_get_interrupt(CPUState *env)
     if (!(s->spurious_vec & APIC_SV_ENABLE))
         return -1;
 
     if (!(s->spurious_vec & APIC_SV_ENABLE))
         return -1;
 

-    /* XXX: spurious IRQ handling */
-    intno = get_highest_priority_int(s->irr);
-    if (intno < 0)
+    intno = apic_irq_pending(s);
+
+    if (intno == 0) {

         return -1;
         return -1;

-    if (s->tpr && intno <= s->tpr)
+    } else if (intno < 0) {

         return s->spurious_vec & 0xff;
         return s->spurious_vec & 0xff;

+    }

     reset_bit(s->irr, intno);
     set_bit(s->isr, intno);
     apic_update_irq(s);
     return intno;
 }
 
     reset_bit(s->irr, intno);
     set_bit(s->isr, intno);
     apic_update_irq(s);
     return intno;
 }
 

-int apic_accept_pic_intr(CPUState *env)
+int apic_accept_pic_intr(DeviceState *d)

 {
 {

-    APICState *s = env->apic_state;
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);

     uint32_t lvt0;
 
     if (!s)
     uint32_t lvt0;
 
     if (!s)


@@ -531,7 +642,7 @@ static uint32_t apic_get_current_count(APICState *s)
 {
     int64_t d;
     uint32_t val;
 {
     int64_t d;
     uint32_t val;

-    d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
+    d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>

         s->count_shift;
     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
         /* periodic */
         s->count_shift;
     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
         /* periodic */


@@ -574,7 +685,7 @@ static void apic_timer(void *opaque)
 {
     APICState *s = opaque;
 
 {
     APICState *s = opaque;
 

-    apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
+    apic_local_deliver(s, APIC_LVT_TIMER);

     apic_timer_update(s, s->next_time);
 }
 
     apic_timer_update(s, s->next_time);
 }
 


@@ -598,15 +709,16 @@ static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 
 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 {
 
 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 {

-    CPUState *env;
+    DeviceState *d;

     APICState *s;
     uint32_t val;
     int index;
 
     APICState *s;
     uint32_t val;
     int index;
 

-    env = cpu_single_env;
-    if (!env)
+    d = cpu_get_current_apic();
+    if (!d) {

         return 0;
         return 0;

-    s = env->apic_state;
+    }
+    s = DO_UPCAST(APICState, busdev.qdev, d);

 
     index = (addr >> 4) & 0xff;
     switch(index) {
 
     index = (addr >> 4) & 0xff;
     switch(index) {


@@ -671,28 +783,44 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
         val = 0;
         break;
     }
         val = 0;
         break;
     }

-#ifdef DEBUG_APIC
-    printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
-#endif
+    trace_apic_mem_readl(addr, val);

     return val;
 }
 
     return val;
 }
 

+static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
+{
+    uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
+    uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
+    uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
+    uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
+    uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
+    /* XXX: Ignore redirection hint. */
+    apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
+}
+

 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 {

-    CPUState *env;
+    DeviceState *d;

     APICState *s;
     APICState *s;

-    int index;
+    int index = (addr >> 4) & 0xff;
+    if (addr > 0xfff || !index) {
+        /* MSI and MMIO APIC are at the same memory location,
+         * but actually not on the global bus: MSI is on PCI bus
+         * APIC is connected directly to the CPU.
+         * Mapping them on the global bus happens to work because
+         * MSI registers are reserved in APIC MMIO and vice versa. */
+        apic_send_msi(addr, val);
+        return;
+    }

 
 

-    env = cpu_single_env;
-    if (!env)
+    d = cpu_get_current_apic();
+    if (!d) {

         return;
         return;

-    s = env->apic_state;
+    }
+    s = DO_UPCAST(APICState, busdev.qdev, d);

 
 

-#ifdef DEBUG_APIC
-    printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
-#endif
+    trace_apic_mem_writel(addr, val);

 
 

-    index = (addr >> 4) & 0xff;

     switch(index) {
     case 0x02:
         s->id = (val >> 24);
     switch(index) {
     case 0x02:
         s->id = (val >> 24);


@@ -726,9 +854,9 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
         break;
     case 0x30:
         s->icr[0] = val;
         break;
     case 0x30:
         s->icr[0] = val;

-        apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
+        apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,

                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),

-                     (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
+                     (s->icr[0] >> 15) & 1);

         break;
     case 0x31:
         s->icr[1] = val;
         break;
     case 0x31:
         s->icr[1] = val;


@@ -738,12 +866,12 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
             int n = index - 0x32;
             s->lvt[n] = val;
             if (n == APIC_LVT_TIMER)
             int n = index - 0x32;
             s->lvt[n] = val;
             if (n == APIC_LVT_TIMER)

-                apic_timer_update(s, qemu_get_clock(vm_clock));
+                apic_timer_update(s, qemu_get_clock_ns(vm_clock));

         }
         break;
     case 0x38:
         s->initial_count = val;
         }
         break;
     case 0x38:
         s->initial_count = val;

-        s->initial_count_load_time = qemu_get_clock(vm_clock);
+        s->initial_count_load_time = qemu_get_clock_ns(vm_clock);

         apic_timer_update(s, s->initial_count_load_time);
         break;
     case 0x39:
         apic_timer_update(s, s->initial_count_load_time);
         break;
     case 0x39:


@@ -762,39 +890,8 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
     }
 }
 
     }
 }
 

-static void apic_save(QEMUFile *f, void *opaque)
-{
-    APICState *s = opaque;
-    int i;
-
-    qemu_put_be32s(f, &s->apicbase);
-    qemu_put_8s(f, &s->id);
-    qemu_put_8s(f, &s->arb_id);
-    qemu_put_8s(f, &s->tpr);
-    qemu_put_be32s(f, &s->spurious_vec);
-    qemu_put_8s(f, &s->log_dest);
-    qemu_put_8s(f, &s->dest_mode);
-    for (i = 0; i < 8; i++) {
-        qemu_put_be32s(f, &s->isr[i]);
-        qemu_put_be32s(f, &s->tmr[i]);
-        qemu_put_be32s(f, &s->irr[i]);
-    }
-    for (i = 0; i < APIC_LVT_NB; i++) {
-        qemu_put_be32s(f, &s->lvt[i]);
-    }
-    qemu_put_be32s(f, &s->esr);
-    qemu_put_be32s(f, &s->icr[0]);
-    qemu_put_be32s(f, &s->icr[1]);
-    qemu_put_be32s(f, &s->divide_conf);
-    qemu_put_be32(f, s->count_shift);
-    qemu_put_be32s(f, &s->initial_count);
-    qemu_put_be64(f, s->initial_count_load_time);
-    qemu_put_be64(f, s->next_time);
-
-    qemu_put_timer(f, s->timer);
-}
-
-static int apic_load(QEMUFile *f, void *opaque, int version_id)
+/* This function is only used for old state version 1 and 2 */
+static int apic_load_old(QEMUFile *f, void *opaque, int version_id)

 {
     APICState *s = opaque;
     int i;
 {
     APICState *s = opaque;
     int i;


@@ -832,16 +929,48 @@ static int apic_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
     return 0;
 }
 

-static void apic_reset(void *opaque)
+static const VMStateDescription vmstate_apic = {
+    .name = "apic",
+    .version_id = 3,
+    .minimum_version_id = 3,
+    .minimum_version_id_old = 1,
+    .load_state_old = apic_load_old,
+    .fields      = (VMStateField []) {
+        VMSTATE_UINT32(apicbase, APICState),
+        VMSTATE_UINT8(id, APICState),
+        VMSTATE_UINT8(arb_id, APICState),
+        VMSTATE_UINT8(tpr, APICState),
+        VMSTATE_UINT32(spurious_vec, APICState),
+        VMSTATE_UINT8(log_dest, APICState),
+        VMSTATE_UINT8(dest_mode, APICState),
+        VMSTATE_UINT32_ARRAY(isr, APICState, 8),
+        VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
+        VMSTATE_UINT32_ARRAY(irr, APICState, 8),
+        VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
+        VMSTATE_UINT32(esr, APICState),
+        VMSTATE_UINT32_ARRAY(icr, APICState, 2),
+        VMSTATE_UINT32(divide_conf, APICState),
+        VMSTATE_INT32(count_shift, APICState),
+        VMSTATE_UINT32(initial_count, APICState),
+        VMSTATE_INT64(initial_count_load_time, APICState),
+        VMSTATE_INT64(next_time, APICState),
+        VMSTATE_TIMER(timer, APICState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void apic_reset(DeviceState *d)

 {
 {

-    APICState *s = opaque;
+    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
+    int bsp;

 
 

+    bsp = cpu_is_bsp(s->cpu_env);

     s->apicbase = 0xfee00000 |
     s->apicbase = 0xfee00000 |

-        (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
+        (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;

 
 

-    apic_init_ipi(s);
+    apic_init_reset(d);

 
 

-    if (s->id == 0) {
+    if (bsp) {

         /*
          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
          * time typically by BIOS, so PIC interrupt can be delivered to the
         /*
          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
          * time typically by BIOS, so PIC interrupt can be delivered to the


@@ -851,255 +980,49 @@ static void apic_reset(void *opaque)
     }
 }
 
     }
 }
 

-static CPUReadMemoryFunc *apic_mem_read[3] = {
-    apic_mem_readb,
-    apic_mem_readw,
-    apic_mem_readl,
+static const MemoryRegionOps apic_io_ops = {
+    .old_mmio = {
+        .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
+        .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
+    },
+    .endianness = DEVICE_NATIVE_ENDIAN,

 };
 
 };
 

-static CPUWriteMemoryFunc *apic_mem_write[3] = {
-    apic_mem_writeb,
-    apic_mem_writew,
-    apic_mem_writel,
-};
-
-int apic_init(CPUState *env)
+static int apic_init1(SysBusDevice *dev)

 {
 {

-    APICState *s;
+    APICState *s = FROM_SYSBUS(APICState, dev);
+    static int last_apic_idx;

 
 

-    if (last_apic_id >= MAX_APICS)
+    if (last_apic_idx >= MAX_APICS) {

         return -1;
         return -1;

-    s = qemu_mallocz(sizeof(APICState));
-    if (!s)
-        return -1;
-    env->apic_state = s;
-    s->id = last_apic_id++;
-    env->cpuid_apic_id = s->id;
-    s->cpu_env = env;
-
-    apic_reset(s);
-
-    /* XXX: mapping more APICs at the same memory location */
-    if (apic_io_memory == 0) {
-        /* NOTE: the APIC is directly connected to the CPU - it is not
-           on the global memory bus. */
-        apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
-                                                apic_mem_write, NULL);
-        cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
-                                     apic_io_memory);

     }
     }

-    s->timer = qemu_new_timer(vm_clock, apic_timer, s);
-
-    register_savevm("apic", s->id, 2, apic_save, apic_load, s);
-    qemu_register_reset(apic_reset, s);
+    memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
+                          MSI_ADDR_SIZE);
+    sysbus_init_mmio_region(dev, &s->io_memory);

 
 

-    local_apics[s->id] = s;
+    s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
+    s->idx = last_apic_idx++;
+    local_apics[s->idx] = s;

     return 0;
 }
 
     return 0;
 }
 

-static void ioapic_service(IOAPICState *s)
-{
-    uint8_t i;
-    uint8_t trig_mode;
-    uint8_t vector;
-    uint8_t delivery_mode;
-    uint32_t mask;
-    uint64_t entry;
-    uint8_t dest;
-    uint8_t dest_mode;
-    uint8_t polarity;
-    uint32_t deliver_bitmask[MAX_APIC_WORDS];
-
-    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
-        mask = 1 << i;
-        if (s->irr & mask) {
-            entry = s->ioredtbl[i];
-            if (!(entry & APIC_LVT_MASKED)) {
-                trig_mode = ((entry >> 15) & 1);
-                dest = entry >> 56;
-                dest_mode = (entry >> 11) & 1;
-                delivery_mode = (entry >> 8) & 7;
-                polarity = (entry >> 13) & 1;
-                if (trig_mode == APIC_TRIGGER_EDGE)
-                    s->irr &= ~mask;
-                if (delivery_mode == APIC_DM_EXTINT)
-                    vector = pic_read_irq(isa_pic);
-                else
-                    vector = entry & 0xff;
-
-                apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
-                apic_bus_deliver(deliver_bitmask, delivery_mode,
-                                 vector, polarity, trig_mode);
-            }
-        }
-    }
-}
-
-void ioapic_set_irq(void *opaque, int vector, int level)
-{
-    IOAPICState *s = opaque;
-
-    if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
-        uint32_t mask = 1 << vector;
-        uint64_t entry = s->ioredtbl[vector];
-
-        if ((entry >> 15) & 1) {
-            /* level triggered */
-            if (level) {
-                s->irr |= mask;
-                ioapic_service(s);
-            } else {
-                s->irr &= ~mask;
-            }
-        } else {
-            /* edge triggered */
-            if (level) {
-                s->irr |= mask;
-                ioapic_service(s);
-            }
-        }
-    }
-}
-
-static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
-{
-    IOAPICState *s = opaque;
-    int index;
-    uint32_t val = 0;
-
-    addr &= 0xff;
-    if (addr == 0x00) {
-        val = s->ioregsel;
-    } else if (addr == 0x10) {
-        switch (s->ioregsel) {
-            case 0x00:
-                val = s->id << 24;
-                break;
-            case 0x01:
-                val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
-                break;
-            case 0x02:
-                val = 0;
-                break;
-            default:
-                index = (s->ioregsel - 0x10) >> 1;
-                if (index >= 0 && index < IOAPIC_NUM_PINS) {
-                    if (s->ioregsel & 1)
-                        val = s->ioredtbl[index] >> 32;
-                    else
-                        val = s->ioredtbl[index] & 0xffffffff;
-                }
-        }
-#ifdef DEBUG_IOAPIC
-        printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
-#endif
-    }
-    return val;
-}
-
-static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    IOAPICState *s = opaque;
-    int index;
-
-    addr &= 0xff;
-    if (addr == 0x00)  {
-        s->ioregsel = val;
-        return;
-    } else if (addr == 0x10) {
-#ifdef DEBUG_IOAPIC
-        printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
-#endif
-        switch (s->ioregsel) {
-            case 0x00:
-                s->id = (val >> 24) & 0xff;
-                return;
-            case 0x01:
-            case 0x02:
-                return;
-            default:
-                index = (s->ioregsel - 0x10) >> 1;
-                if (index >= 0 && index < IOAPIC_NUM_PINS) {
-                    if (s->ioregsel & 1) {
-                        s->ioredtbl[index] &= 0xffffffff;
-                        s->ioredtbl[index] |= (uint64_t)val << 32;
-                    } else {
-                        s->ioredtbl[index] &= ~0xffffffffULL;
-                        s->ioredtbl[index] |= val;
-                    }
-                    ioapic_service(s);
-                }
-        }
-    }
-}
-
-static void ioapic_save(QEMUFile *f, void *opaque)
-{
-    IOAPICState *s = opaque;
-    int i;
-
-    qemu_put_8s(f, &s->id);
-    qemu_put_8s(f, &s->ioregsel);
-    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
-        qemu_put_be64s(f, &s->ioredtbl[i]);
-    }
-}
-
-static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
-{
-    IOAPICState *s = opaque;
-    int i;
-
-    if (version_id != 1)
-        return -EINVAL;
-
-    qemu_get_8s(f, &s->id);
-    qemu_get_8s(f, &s->ioregsel);
-    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
-        qemu_get_be64s(f, &s->ioredtbl[i]);
+static SysBusDeviceInfo apic_info = {
+    .init = apic_init1,
+    .qdev.name = "apic",
+    .qdev.size = sizeof(APICState),
+    .qdev.vmsd = &vmstate_apic,
+    .qdev.reset = apic_reset,
+    .qdev.no_user = 1,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_UINT8("id", APICState, id, -1),
+        DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
+        DEFINE_PROP_END_OF_LIST(),

     }
     }

-    return 0;
-}
-
-static void ioapic_reset(void *opaque)
-{
-    IOAPICState *s = opaque;
-    int i;
-
-    memset(s, 0, sizeof(*s));
-    for(i = 0; i < IOAPIC_NUM_PINS; i++)
-        s->ioredtbl[i] = 1 << 16; /* mask LVT */
-}
-
-static CPUReadMemoryFunc *ioapic_mem_read[3] = {
-    ioapic_mem_readl,
-    ioapic_mem_readl,
-    ioapic_mem_readl,
-};
-
-static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
-    ioapic_mem_writel,
-    ioapic_mem_writel,
-    ioapic_mem_writel,

 };
 
 };
 

-IOAPICState *ioapic_init(void)
+static void apic_register_devices(void)

 {
 {

-    IOAPICState *s;
-    int io_memory;
-
-    s = qemu_mallocz(sizeof(IOAPICState));
-    if (!s)
-        return NULL;
-    ioapic_reset(s);
-    s->id = last_apic_id++;
-
-    io_memory = cpu_register_io_memory(0, ioapic_mem_read,
-                                       ioapic_mem_write, s);
-    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
-
-    register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
-    qemu_register_reset(ioapic_reset, s);
-
-    return s;
+    sysbus_register_withprop(&apic_info);

 }
 }

+
+device_init(apic_register_devices)