ARM CP15 tls fix

[qemu.git] / target-mips / TODO

diff --git a/target-mips/TODO b/target-mips/TODO
index bc287f63a516d0f15c9992a4e98efa89662206b1..9101881a97cb2584d31d9b1341c62366e0c93189 100644 (file)
--- a/target-mips/TODO
+++ b/target-mips/TODO
@@ -4,7 +4,6 @@ Unsolved issues/bugs in the mips/mipsel backend
 General
 -------
 - Unimplemented ASEs:
-  - MIPS16
   - MDMX
   - SmartMIPS
   - DSP r1
@@ -29,6 +28,7 @@ General
   To cope with these differences, Qemu currently flushes the TLB at
   each ASID change. Using the MMU modes to implement ASIDs hinges on
   implementing the global bit efficiently.
+- save/restore of the CPU state is not implemented (see machine.c).
 
 MIPS64
 ------
@@ -36,7 +36,8 @@ MIPS64
 
 "Generic" 4Kc system emulation
 ------------------------------
-- Doesn't correspond to any real hardware.
+- Doesn't correspond to any real hardware. Should be removed some day,
+  U-Boot is the last remaining user.
 
 PICA 61 system emulation
 ------------------------
@@ -45,5 +46,7 @@ PICA 61 system emulation
 MALTA system emulation
 ----------------------
 - We fake firmware support instead of doing the real thing
-- Real firmware falls over when trying to init RAM, presumably due
-  to lacking system controller emulation.
+- Real firmware (YAMON) falls over when trying to init RAM, presumably
+  due to lacking system controller emulation.
+- Bonito system controller not implemented
+- MSC1 system controller not implemented