Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2016-02-09' into staging

[qemu.git] / target-mips / mips-defs.h

diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3bd556e32410636a6b6ef70cd1b3fd680a..53b185ebd3851e995aeea0229934d9985ee170dd 100644 (file)
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -10,11 +10,11 @@
 
 #if defined(TARGET_MIPS64)
 #define TARGET_LONG_BITS 64
 
 #if defined(TARGET_MIPS64)
 #define TARGET_LONG_BITS 64

-#define TARGET_PHYS_ADDR_SPACE_BITS 36
-#define TARGET_VIRT_ADDR_SPACE_BITS 42
+#define TARGET_PHYS_ADDR_SPACE_BITS 48
+#define TARGET_VIRT_ADDR_SPACE_BITS 48

 #else
 #define TARGET_LONG_BITS 32
 #else
 #define TARGET_LONG_BITS 32

-#define TARGET_PHYS_ADDR_SPACE_BITS 36
+#define TARGET_PHYS_ADDR_SPACE_BITS 40

 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 


@@ -29,16 +29,23 @@
 #define                ISA_MIPS32R2    0x00000040
 #define                ISA_MIPS64      0x00000080
 #define                ISA_MIPS64R2    0x00000100
 #define                ISA_MIPS32R2    0x00000040
 #define                ISA_MIPS64      0x00000080
 #define                ISA_MIPS64R2    0x00000100

+#define   ISA_MIPS32R3  0x00000200
+#define   ISA_MIPS64R3  0x00000400
+#define   ISA_MIPS32R5  0x00000800
+#define   ISA_MIPS64R5  0x00001000
+#define   ISA_MIPS32R6  0x00002000
+#define   ISA_MIPS64R6  0x00004000

 
 /* MIPS ASEs. */
 
 /* MIPS ASEs. */

-#define                ASE_MIPS16      0x00001000
-#define                ASE_MIPS3D      0x00002000
-#define                ASE_MDMX        0x00004000
-#define                ASE_DSP         0x00008000
-#define                ASE_DSPR2       0x00010000
-#define                ASE_MT          0x00020000
-#define                ASE_SMARTMIPS   0x00040000
-#define        ASE_MICROMIPS   0x00080000
+#define   ASE_MIPS16    0x00010000
+#define   ASE_MIPS3D    0x00020000
+#define   ASE_MDMX      0x00040000
+#define   ASE_DSP       0x00080000
+#define   ASE_DSPR2     0x00100000
+#define   ASE_MT        0x00200000
+#define   ASE_SMARTMIPS 0x00400000
+#define   ASE_MICROMIPS 0x00800000
+#define   ASE_MSA       0x01000000

 
 /* Chip specific instructions. */
 #define                INSN_LOONGSON2E  0x20000000
 
 /* Chip specific instructions. */
 #define                INSN_LOONGSON2E  0x20000000


@@ -64,6 +71,18 @@
 #define                CPU_MIPS32R2    (CPU_MIPS32 | ISA_MIPS32R2)
 #define                CPU_MIPS64R2    (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
 
 #define                CPU_MIPS32R2    (CPU_MIPS32 | ISA_MIPS32R2)
 #define                CPU_MIPS64R2    (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
 

+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
+
+/* MIPS Technologies "Release 6" */
+#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
+#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
+

 /* Strictly follow the architecture standard:
    - Disallow "special" instruction handling for PMON/SPIM.
    Note that we still maintain Count/Compare to match the host clock. */
 /* Strictly follow the architecture standard:
    - Disallow "special" instruction handling for PMON/SPIM.
    Note that we still maintain Count/Compare to match the host clock. */