#include "cpu.h"
#include "trace.h"
-#include "exec-memory.h"
+#include "exec/address-spaces.h"
/* Sparc MMU emulation */
#if defined(CONFIG_USER_ONLY)
-int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
+int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
int mmu_idx)
{
if (rw & 2) {
}
};
-static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
int access_perms = 0;
- target_phys_addr_t pde_ptr;
+ hwaddr pde_ptr;
uint32_t pde;
int error_code = 0, is_dirty, is_user;
unsigned long page_offset;
case 3: /* Reserved */
return (3 << 8) | (4 << 2);
case 2: /* L3 PTE */
- page_offset = (address & TARGET_PAGE_MASK) &
- (TARGET_PAGE_SIZE - 1);
+ page_offset = 0;
}
*page_size = TARGET_PAGE_SIZE;
break;
case 2: /* L2 PTE */
- page_offset = address & 0x3ffff;
+ page_offset = address & 0x3f000;
*page_size = 0x40000;
}
break;
case 2: /* L1 PTE */
- page_offset = address & 0xffffff;
+ page_offset = address & 0xfff000;
*page_size = 0x1000000;
}
}
/* Even if large ptes, we map only one 4KB page in the cache to
avoid filling it too fast */
- *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
+ *physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
return error_code;
}
/* Perform address translation */
-int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
int mmu_idx)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
target_ulong vaddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
+ address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index,
address, rw, mmu_idx, &page_size);
+ vaddr = address;
if (error_code == 0) {
- vaddr = address & TARGET_PAGE_MASK;
- paddr &= TARGET_PAGE_MASK;
#ifdef DEBUG_MMU
printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
TARGET_FMT_lx "\n", address, paddr, vaddr);
permissions. If no mapping is available, redirect accesses to
neverland. Fake/overridden mappings will be flushed when
switching to normal mode. */
- vaddr = address & TARGET_PAGE_MASK;
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
}
-target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
+target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
{
- target_phys_addr_t pde_ptr;
+ hwaddr pde_ptr;
uint32_t pde;
/* Context base + context number */
- pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
+ pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
(env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
return 0;
}
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
{
target_ulong va, va1, va2;
unsigned int n, m, o;
- target_phys_addr_t pde_ptr, pa;
+ hwaddr pde_ptr, pa;
uint32_t pde;
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
- (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
+ (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
* reads (and only reads) in stack frames as if windows were flushed. We assume
* that the sparc ABI is followed.
*/
-int target_memory_rw_debug(CPUState *env, target_ulong addr,
+int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int i;
#else /* !TARGET_SPARC64 */
/* 41 bit physical address space */
-static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
+static inline hwaddr ultrasparc_truncate_physical(uint64_t x)
{
return x & 0x1ffffffffffULL;
}
entry size */
static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
uint64_t address, uint64_t context,
- target_phys_addr_t *physical)
+ hwaddr *physical)
{
uint64_t mask;
return 0;
}
-static int get_physical_address_data(CPUState *env,
- target_phys_addr_t *physical, int *prot,
+static int get_physical_address_data(CPUSPARCState *env,
+ hwaddr *physical, int *prot,
target_ulong address, int rw, int mmu_idx)
{
unsigned int i;
return 1;
}
-static int get_physical_address_code(CPUState *env,
- target_phys_addr_t *physical, int *prot,
+static int get_physical_address_code(CPUSPARCState *env,
+ hwaddr *physical, int *prot,
target_ulong address, int mmu_idx)
{
unsigned int i;
return 1;
}
-static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
}
/* Perform address translation */
-int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
int mmu_idx)
{
- target_ulong virt_addr, vaddr;
- target_phys_addr_t paddr;
+ target_ulong vaddr;
+ hwaddr paddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
+ address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index,
address, rw, mmu_idx, &page_size);
if (error_code == 0) {
- virt_addr = address & TARGET_PAGE_MASK;
- vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
- (TARGET_PAGE_SIZE - 1));
+ vaddr = address;
trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
env->dmmu.mmu_primary_context,
return 1;
}
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
{
unsigned int i;
const char *mask;
#endif /* TARGET_SPARC64 */
-static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
+static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
target_ulong addr, int rw, int mmu_idx)
{
target_ulong page_size;
}
#if defined(TARGET_SPARC64)
-target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
+hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int mmu_idx)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
return -1;
}
#endif
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
int mmu_idx = cpu_mmu_index(env);
MemoryRegionSection section;
projects / qemu.git / blobdiff