Replace gcc variadic macro extension with C99 version

[qemu.git] / hw / esp.c

diff --git a/hw/esp.c b/hw/esp.c
index 1843fb895c999b9c4d289668bd58cc3bfef2f00c..17b8f9635b2d4c816d87705a0d78460b3d9e7025 100644 (file)
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -38,14 +38,17 @@
  */
 
 #ifdef DEBUG_ESP
-#define DPRINTF(fmt, args...) \
-do { printf("ESP: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...)                                       \
+    do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF(fmt, args...) do {} while (0)
+#define DPRINTF(fmt, ...) do {} while (0)
 #endif
 
+#define ESP_ERROR(fmt, ...)                                             \
+    do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
+
 #define ESP_REGS 16
-#define TI_BUFSZ 32
+#define TI_BUFSZ 16
 
 typedef struct ESPState ESPState;
 
@@ -120,8 +123,8 @@ struct ESPState {
 #define STAT_DI 0x01
 #define STAT_CD 0x02
 #define STAT_ST 0x03
-#define STAT_MI 0x06
-#define STAT_MO 0x07
+#define STAT_MO 0x06
+#define STAT_MI 0x07
 #define STAT_PIO_MASK 0x06
 
 #define STAT_TC 0x10
@@ -129,6 +132,8 @@ struct ESPState {
 #define STAT_GE 0x40
 #define STAT_INT 0x80
 
+#define BUSID_DID 0x07
+
 #define INTR_FC 0x08
 #define INTR_BS 0x10
 #define INTR_DC 0x20
@@ -139,8 +144,6 @@ struct ESPState {
 
 #define CFG1_RESREPT 0x40
 
-#define CFG2_MASK 0x15
-
 #define TCHI_FAS100A 0x4
 
 static void esp_raise_irq(ESPState *s)
@@ -164,16 +167,16 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf)
     uint32_t dmalen;
     int target;
 
-    dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
-    target = s->wregs[ESP_WBUSID] & 7;
-    DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
+    target = s->wregs[ESP_WBUSID] & BUSID_DID;
     if (s->dma) {
+        dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
         s->dma_memory_read(s->dma_opaque, buf, dmalen);
     } else {
+        dmalen = s->ti_size;
+        memcpy(buf, s->ti_buf, dmalen);
         buf[0] = 0;
-        memcpy(&buf[1], s->ti_buf, dmalen);
-        dmalen++;
     }
+    DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
 
     s->ti_size = 0;
     s->ti_rptr = 0;
@@ -318,7 +321,7 @@ static void esp_do_dma(ESPState *s)
         } else {
             s->current_dev->read_data(s->current_dev, 0);
             /* If there is still data to be read from the device then
-               complete the DMA operation immeriately.  Otherwise defer
+               complete the DMA operation immediately.  Otherwise defer
                until the scsi layer has completed.  */
             if (s->dma_left == 0 && s->ti_size > 0) {
                 esp_dma_done(s);
@@ -407,6 +410,8 @@ static void esp_reset(void *opaque)
     s->ti_wptr = 0;
     s->dma = 0;
     s->do_cmd = 0;
+
+    s->rregs[ESP_CFG1] = 7;
 }
 
 static void parent_esp_reset(void *opaque, int irq, int level)
@@ -420,15 +425,15 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
     ESPState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
+    saddr = addr >> s->it_shift;
     DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
     switch (saddr) {
     case ESP_FIFO:
         if (s->ti_size > 0) {
             s->ti_size--;
             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
-                /* Data in/out.  */
-                fprintf(stderr, "esp: PIO data read not implemented\n");
+                /* Data out.  */
+                ESP_ERROR("PIO data read not implemented\n");
                 s->rregs[ESP_FIFO] = 0;
             } else {
                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
@@ -456,7 +461,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
     ESPState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
+    saddr = addr >> s->it_shift;
     DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
             val);
     switch (saddr) {
@@ -467,11 +472,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
     case ESP_FIFO:
         if (s->do_cmd) {
             s->cmdbuf[s->cmdlen++] = val & 0xff;
-        } else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
-            uint8_t buf;
-            buf = val & 0xff;
-            s->ti_size--;
-            fprintf(stderr, "esp: PIO data write not implemented\n");
+        } else if (s->ti_size == TI_BUFSZ - 1) {
+            ESP_ERROR("fifo overrun\n");
         } else {
             s->ti_size++;
             s->ti_buf[s->ti_wptr++] = val & 0xff;
@@ -496,6 +498,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
             //s->ti_size = 0;
             s->rregs[ESP_RINTR] = INTR_FC;
             s->rregs[ESP_RSEQ] = 0;
+            s->rregs[ESP_RFLAGS] = 0;
             break;
         case CMD_RESET:
             DPRINTF("Chip reset (%2.2x)\n", val);
@@ -514,6 +517,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
         case CMD_ICCS:
             DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
             write_response(s);
+            s->rregs[ESP_RINTR] = INTR_FC;
+            s->rregs[ESP_RSTAT] |= STAT_MI;
             break;
         case CMD_MSGACC:
             DPRINTF("Message Accepted (%2.2x)\n", val);
@@ -534,9 +539,10 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
             break;
         case CMD_ENSEL:
             DPRINTF("Enable selection (%2.2x)\n", val);
+            s->rregs[ESP_RINTR] = 0;
             break;
         default:
-            DPRINTF("Unhandled ESP command (%2.2x)\n", val);
+            ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
             break;
         }
         break;
@@ -547,14 +553,12 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
         break;
     case ESP_WCCF ... ESP_WTEST:
         break;
-    case ESP_CFG2:
-        s->rregs[saddr] = val & CFG2_MASK;
-        break;
-    case ESP_CFG3 ... ESP_RES4:
+    case ESP_CFG2 ... ESP_RES4:
         s->rregs[saddr] = val;
         break;
     default:
-        break;
+        ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
+        return;
     }
     s->wregs[saddr] = val;
 }
@@ -568,7 +572,7 @@ static CPUReadMemoryFunc *esp_mem_read[3] = {
 static CPUWriteMemoryFunc *esp_mem_write[3] = {
     esp_mem_writeb,
     NULL,
-    NULL,
+    esp_mem_writeb,
 };
 
 static void esp_save(QEMUFile *f, void *opaque)
@@ -577,7 +581,7 @@ static void esp_save(QEMUFile *f, void *opaque)
 
     qemu_put_buffer(f, s->rregs, ESP_REGS);
     qemu_put_buffer(f, s->wregs, ESP_REGS);
-    qemu_put_be32s(f, (uint32_t *)&s->ti_size);
+    qemu_put_sbe32s(f, &s->ti_size);
     qemu_put_be32s(f, &s->ti_rptr);
     qemu_put_be32s(f, &s->ti_wptr);
     qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
@@ -599,7 +603,7 @@ static int esp_load(QEMUFile *f, void *opaque, int version_id)
 
     qemu_get_buffer(f, s->rregs, ESP_REGS);
     qemu_get_buffer(f, s->wregs, ESP_REGS);
-    qemu_get_be32s(f, (uint32_t *)&s->ti_size);
+    qemu_get_sbe32s(f, &s->ti_size);
     qemu_get_be32s(f, &s->ti_rptr);
     qemu_get_be32s(f, &s->ti_wptr);
     qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
@@ -619,6 +623,8 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
 
     if (id < 0) {
         for (id = 0; id < ESP_MAX_DEVS; id++) {
+            if (id == (s->rregs[ESP_CFG1] & 0x7))
+                continue;
             if (s->scsi_dev[id] == NULL)
                 break;
         }
@@ -647,8 +653,6 @@ void *esp_init(target_phys_addr_t espaddr, int it_shift,
     int esp_io_memory;
 
     s = qemu_mallocz(sizeof(ESPState));
-    if (!s)
-        return NULL;
 
     s->irq = irq;
     s->it_shift = it_shift;