#define hypervisor(dc) 0
#endif
#else
-#define supervisor(dc) (dc->mem_idx >= 1)
+#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
#ifdef TARGET_SPARC64
-#define hypervisor(dc) (dc->mem_idx == 2)
+#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
#else
#endif
#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2)
+static TCGv_i32 gen_add32_carry32(void)
{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_movi_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2);
- tcg_gen_mov_tl(dst, cpu_cc_dst);
+ TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
+
+ /* Carry is computed from a previous add: (dst < src) */
+#if TARGET_LONG_BITS == 64
+ cc_src1_32 = tcg_temp_new_i32();
+ cc_src2_32 = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_dst);
+ tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src);
+#else
+ cc_src1_32 = cpu_cc_dst;
+ cc_src2_32 = cpu_cc_src;
+#endif
+
+ carry_32 = tcg_temp_new_i32();
+ tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
+
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free_i32(cc_src1_32);
+ tcg_temp_free_i32(cc_src2_32);
+#endif
+
+ return carry_32;
}
-static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
+static TCGv_i32 gen_sub32_carry32(void)
{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_mov_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
- tcg_gen_mov_tl(dst, cpu_cc_dst);
+ TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
+
+ /* Carry is computed from a previous borrow: (src1 < src2) */
+#if TARGET_LONG_BITS == 64
+ cc_src1_32 = tcg_temp_new_i32();
+ cc_src2_32 = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_src);
+ tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src2);
+#else
+ cc_src1_32 = cpu_cc_src;
+ cc_src2_32 = cpu_cc_src2;
+#endif
+
+ carry_32 = tcg_temp_new_i32();
+ tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
+
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free_i32(cc_src1_32);
+ tcg_temp_free_i32(cc_src2_32);
+#endif
+
+ return carry_32;
+}
+
+static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
+ TCGv src2, int update_cc)
+{
+ TCGv_i32 carry_32;
+ TCGv carry;
+
+ switch (dc->cc_op) {
+ case CC_OP_DIV:
+ case CC_OP_LOGIC:
+ /* Carry is known to be zero. Fall back to plain ADD. */
+ if (update_cc) {
+ gen_op_add_cc(dst, src1, src2);
+ } else {
+ tcg_gen_add_tl(dst, src1, src2);
+ }
+ return;
+
+ case CC_OP_ADD:
+ case CC_OP_TADD:
+ case CC_OP_TADDTV:
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ {
+ /* For 32-bit hosts, we can re-use the host's hardware carry
+ generation by using an ADD2 opcode. We discard the low
+ part of the output. Ideally we'd combine this operation
+ with the add that generated the carry in the first place. */
+ TCGv dst_low = tcg_temp_new();
+ tcg_gen_op6_i32(INDEX_op_add2_i32, dst_low, dst,
+ cpu_cc_src, src1, cpu_cc_src2, src2);
+ tcg_temp_free(dst_low);
+ goto add_done;
+ }
+#endif
+ carry_32 = gen_add32_carry32();
+ break;
+
+ case CC_OP_SUB:
+ case CC_OP_TSUB:
+ case CC_OP_TSUBTV:
+ carry_32 = gen_sub32_carry32();
+ break;
+
+ default:
+ /* We need external help to produce the carry. */
+ carry_32 = tcg_temp_new_i32();
+ gen_helper_compute_C_icc(carry_32);
+ break;
+ }
+
+#if TARGET_LONG_BITS == 64
+ carry = tcg_temp_new();
+ tcg_gen_extu_i32_i64(carry, carry_32);
+#else
+ carry = carry_32;
+#endif
+
+ tcg_gen_add_tl(dst, src1, src2);
+ tcg_gen_add_tl(dst, dst, carry);
+
+ tcg_temp_free_i32(carry_32);
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free(carry);
+#endif
+
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ add_done:
+#endif
+ if (update_cc) {
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+ dc->cc_op = CC_OP_ADDX;
+ }
}
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2)
+static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
+ TCGv src2, int update_cc)
{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_movi_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2);
- tcg_gen_mov_tl(dst, cpu_cc_dst);
-}
+ TCGv_i32 carry_32;
+ TCGv carry;
-static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
-{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_mov_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
- tcg_gen_mov_tl(dst, cpu_cc_dst);
+ switch (dc->cc_op) {
+ case CC_OP_DIV:
+ case CC_OP_LOGIC:
+ /* Carry is known to be zero. Fall back to plain SUB. */
+ if (update_cc) {
+ gen_op_sub_cc(dst, src1, src2);
+ } else {
+ tcg_gen_sub_tl(dst, src1, src2);
+ }
+ return;
+
+ case CC_OP_ADD:
+ case CC_OP_TADD:
+ case CC_OP_TADDTV:
+ carry_32 = gen_add32_carry32();
+ break;
+
+ case CC_OP_SUB:
+ case CC_OP_TSUB:
+ case CC_OP_TSUBTV:
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ {
+ /* For 32-bit hosts, we can re-use the host's hardware carry
+ generation by using a SUB2 opcode. We discard the low
+ part of the output. Ideally we'd combine this operation
+ with the add that generated the carry in the first place. */
+ TCGv dst_low = tcg_temp_new();
+ tcg_gen_op6_i32(INDEX_op_sub2_i32, dst_low, dst,
+ cpu_cc_src, src1, cpu_cc_src2, src2);
+ tcg_temp_free(dst_low);
+ goto sub_done;
+ }
+#endif
+ carry_32 = gen_sub32_carry32();
+ break;
+
+ default:
+ /* We need external help to produce the carry. */
+ carry_32 = tcg_temp_new_i32();
+ gen_helper_compute_C_icc(carry_32);
+ break;
+ }
+
+#if TARGET_LONG_BITS == 64
+ carry = tcg_temp_new();
+ tcg_gen_extu_i32_i64(carry, carry_32);
+#else
+ carry = carry_32;
+#endif
+
+ tcg_gen_sub_tl(dst, src1, src2);
+ tcg_gen_sub_tl(dst, dst, carry);
+
+ tcg_temp_free_i32(carry_32);
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free(carry);
+#endif
+
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ sub_done:
+#endif
+ if (update_cc) {
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
+ dc->cc_op = CC_OP_SUBX;
+ }
}
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
{
+ TCGv_i32 r_src1, r_src2;
TCGv_i64 r_temp, r_temp2;
+ r_src1 = tcg_temp_new_i32();
+ r_src2 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(r_src1, src1);
+ tcg_gen_trunc_tl_i32(r_src2, src2);
+
r_temp = tcg_temp_new_i64();
r_temp2 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(r_temp, src2);
- tcg_gen_extu_tl_i64(r_temp2, src1);
+ if (sign_ext) {
+ tcg_gen_ext_i32_i64(r_temp, r_src2);
+ tcg_gen_ext_i32_i64(r_temp2, r_src1);
+ } else {
+ tcg_gen_extu_i32_i64(r_temp, r_src2);
+ tcg_gen_extu_i32_i64(r_temp2, r_src1);
+ }
+
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
tcg_gen_shri_i64(r_temp, r_temp2, 32);
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
tcg_temp_free_i64(r_temp);
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
-#ifdef TARGET_SPARC64
- tcg_gen_mov_i64(dst, r_temp2);
-#else
+
tcg_gen_trunc_i64_tl(dst, r_temp2);
-#endif
+
tcg_temp_free_i64(r_temp2);
+
+ tcg_temp_free_i32(r_src1);
+ tcg_temp_free_i32(r_src2);
}
-static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
{
- TCGv_i64 r_temp, r_temp2;
-
- r_temp = tcg_temp_new_i64();
- r_temp2 = tcg_temp_new_i64();
-
- tcg_gen_ext_tl_i64(r_temp, src2);
- tcg_gen_ext_tl_i64(r_temp2, src1);
- tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
+ /* zero-extend truncated operands before multiplication */
+ gen_op_multiply(dst, src1, src2, 0);
+}
- tcg_gen_shri_i64(r_temp, r_temp2, 32);
- tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
- tcg_temp_free_i64(r_temp);
- tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
-#ifdef TARGET_SPARC64
- tcg_gen_mov_i64(dst, r_temp2);
-#else
- tcg_gen_trunc_i64_tl(dst, r_temp2);
-#endif
- tcg_temp_free_i64(r_temp2);
+static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
+{
+ /* sign-extend truncated operands before multiplication */
+ gen_op_multiply(dst, src1, src2, 1);
}
#ifdef TARGET_SPARC64
} else
tcg_gen_mov_tl(cpu_dst, cpu_src1);
}
+
cond = GET_FIELD(insn, 3, 6);
- if (cond == 0x8) {
+ if (cond == 0x8) { /* Trap Always */
save_state(dc, cpu_cond);
if ((dc->def->features & CPU_FEATURE_HYPV) &&
supervisor(dc))
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- gen_helper_raise_exception(cpu_tmp32);
+
+ if (rs2 == 0 &&
+ dc->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
+
+ gen_helper_shutdown();
+
+ } else {
+ gen_helper_raise_exception(cpu_tmp32);
+ }
} else if (cond != 0) {
TCGv r_cond = tcg_temp_new();
int l1;
case 0x10 ... 0x1f: /* implementation-dependent in the
SPARCv8 manual, rdy on the
microSPARC II */
+ /* Read Asr17 */
+ if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
+ TCGv r_const;
+
+ /* Read Asr17 for a Leon3 monoprocessor */
+ r_const = tcg_const_tl((1 << 8)
+ | (dc->def->nwindows - 1));
+ gen_movl_TN_reg(rd, r_const);
+ tcg_temp_free(r_const);
+ break;
+ }
#endif
gen_movl_TN_reg(rd, cpu_y);
break;
}
break;
case 0x8: /* addx, V9 addc */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- if (xop & 0x10) {
- gen_helper_compute_psr();
- gen_op_addxi_cc(cpu_dst, cpu_src1, simm);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
- dc->cc_op = CC_OP_ADDX;
- } else {
- gen_helper_compute_psr();
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- } else {
- if (xop & 0x10) {
- gen_helper_compute_psr();
- gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
- dc->cc_op = CC_OP_ADDX;
- } else {
- gen_helper_compute_psr();
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- }
+ gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
+ (xop & 0x10));
break;
#ifdef TARGET_SPARC64
case 0x9: /* V9 mulx */
}
break;
case 0xc: /* subx, V9 subc */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- if (xop & 0x10) {
- gen_helper_compute_psr();
- gen_op_subxi_cc(cpu_dst, cpu_src1, simm);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
- dc->cc_op = CC_OP_SUBX;
- } else {
- gen_helper_compute_psr();
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- } else {
- if (xop & 0x10) {
- gen_helper_compute_psr();
- gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
- dc->cc_op = CC_OP_SUBX;
- } else {
- gen_helper_compute_psr();
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- }
+ gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
+ (xop & 0x10));
break;
#ifdef TARGET_SPARC64
case 0xd: /* V9 udivx */
#endif
case 0xe: /* udiv */
CHECK_IU_FEATURE(dc, DIV);
- gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV);
+ gen_helper_udiv_cc(cpu_dst, cpu_src1, cpu_src2);
dc->cc_op = CC_OP_DIV;
+ } else {
+ gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
}
break;
case 0xf: /* sdiv */
CHECK_IU_FEATURE(dc, DIV);
- gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV);
+ gen_helper_sdiv_cc(cpu_dst, cpu_src1, cpu_src2);
dc->cc_op = CC_OP_DIV;
+ } else {
+ gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
}
break;
default:
case 6: // pstate
save_state(dc, cpu_cond);
gen_helper_wrpstate(cpu_tmp0);
- gen_op_next_insn();
- tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->npc = DYNAMIC_PC;
break;
case 7: // tl
+ save_state(dc, cpu_cond);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, tl));
+ dc->npc = DYNAMIC_PC;
break;
case 8: // pil
gen_helper_wrpil(cpu_tmp0);
if (rd == 1) {
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
gen_helper_ldxfsr(cpu_tmp64);
- } else
+ } else {
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
+ gen_helper_ldfsr(cpu_tmp32);
+ }
#else
{
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
CHECK_FPU_FEATURE(dc, FLOAT128);
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_ldqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_QT0_fpr(QFPREG(rd));
TCGv_i32 r_const;
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_lddf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_DT0_fpr(DFPREG(rd));
#endif
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 4);
+ dc->npc = DYNAMIC_PC;
break;
case 0x15: /* stba, store byte alternate */
#ifndef TARGET_SPARC64
#endif
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 1);
+ dc->npc = DYNAMIC_PC;
break;
case 0x16: /* stha, store halfword alternate */
#ifndef TARGET_SPARC64
#endif
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 2);
+ dc->npc = DYNAMIC_PC;
break;
case 0x17: /* stda, store double word alternate */
#ifndef TARGET_SPARC64
case 0x1e: /* V9 stxa */
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 8);
+ dc->npc = DYNAMIC_PC;
break;
#endif
default:
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}
gen_op_load_fpr_DT0(DFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stdf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}
projects / qemu.git / blobdiff