* THE SOFTWARE.
*/
-#include <stdio.h>
+#include "sysbus.h"
#include "hw.h"
+//#include "pc.h"
+//#include "etraxfs.h"
#define D(x)
-struct fs_pic_state_t
+#define R_RW_MASK 0
+#define R_R_VECT 1
+#define R_R_MASKED_VECT 2
+#define R_R_NMI 3
+#define R_R_GURU 4
+#define R_MAX 5
+
+struct etrax_pic
{
- CPUState *env;
- target_phys_addr_t base;
-
- uint32_t rw_mask;
- /* Active interrupt lines. */
- uint32_t r_vect;
- /* Active lines, gated through the mask. */
- uint32_t r_masked_vect;
- uint32_t r_nmi;
- uint32_t r_guru;
+ SysBusDevice busdev;
+ MemoryRegion mmio;
+ void *interrupt_vector;
+ qemu_irq parent_irq;
+ qemu_irq parent_nmi;
+ uint32_t regs[R_MAX];
};
-static uint32_t pic_readb (void *opaque, target_phys_addr_t addr)
-{
- return 0;
-}
-static uint32_t pic_readw (void *opaque, target_phys_addr_t addr)
-{
- return 0;
+static void pic_update(struct etrax_pic *fs)
+{
+ uint32_t vector = 0;
+ int i;
+
+ fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
+
+ /* The ETRAX interrupt controller signals interrupts to the core
+ through an interrupt request wire and an irq vector bus. If
+ multiple interrupts are simultaneously active it chooses vector
+ 0x30 and lets the sw choose the priorities. */
+ if (fs->regs[R_R_MASKED_VECT]) {
+ uint32_t mv = fs->regs[R_R_MASKED_VECT];
+ for (i = 0; i < 31; i++) {
+ if (mv & 1) {
+ vector = 0x31 + i;
+ /* Check for multiple interrupts. */
+ if (mv > 1)
+ vector = 0x30;
+ break;
+ }
+ mv >>= 1;
+ }
+ }
+
+ if (fs->interrupt_vector) {
+ /* hack alert: ptr property */
+ *(uint32_t*)(fs->interrupt_vector) = vector;
+ }
+ qemu_set_irq(fs->parent_irq, !!vector);
}
-static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t
+pic_read(void *opaque, hwaddr addr, unsigned int size)
{
- struct fs_pic_state_t *fs = opaque;
- uint32_t rval;
-
- /* Transform this to a relative addr. */
- addr -= fs->base;
- switch (addr)
- {
- case 0x0:
- rval = fs->rw_mask;
- break;
- case 0x4:
- rval = fs->r_vect;
- break;
- case 0x8:
- rval = fs->r_masked_vect;
- break;
- case 0xc:
- rval = fs->r_nmi;
- break;
- case 0x10:
- rval = fs->r_guru;
- break;
- default:
- cpu_abort(fs->env, "invalid PIC register.\n");
- break;
-
- }
- D(printf("%s %x=%x\n", __func__, addr, rval));
- return rval;
-}
+ struct etrax_pic *fs = opaque;
+ uint32_t rval;
-static void
-pic_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
-{
+ rval = fs->regs[addr >> 2];
+ D(printf("%s %x=%x\n", __func__, addr, rval));
+ return rval;
}
-static void
-pic_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void pic_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned int size)
{
-}
+ struct etrax_pic *fs = opaque;
+ D(printf("%s addr=%x val=%x\n", __func__, addr, value));
-static void
-pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
-{
- struct fs_pic_state_t *fs = opaque;
- D(printf("%s addr=%x val=%x\n", __func__, addr, value));
- /* Transform this to a relative addr. */
- addr -= fs->base;
- switch (addr)
- {
- case 0x0:
- fs->rw_mask = value;
- break;
- case 0x4:
- fs->r_vect = value;
- break;
- case 0x8:
- fs->r_masked_vect = value;
- break;
- case 0xc:
- fs->r_nmi = value;
- break;
- case 0x10:
- fs->r_guru = value;
- break;
- default:
- cpu_abort(fs->env, "invalid PIC register.\n");
- break;
- }
+ if (addr == R_RW_MASK) {
+ fs->regs[R_RW_MASK] = value;
+ pic_update(fs);
+ }
}
-static CPUReadMemoryFunc *pic_read[] = {
- &pic_readb,
- &pic_readw,
- &pic_readl,
+static const MemoryRegionOps pic_ops = {
+ .read = pic_read,
+ .write = pic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
};
-static CPUWriteMemoryFunc *pic_write[] = {
- &pic_writeb,
- &pic_writew,
- &pic_writel,
-};
+static void nmi_handler(void *opaque, int irq, int level)
+{
+ struct etrax_pic *fs = (void *)opaque;
+ uint32_t mask;
-void pic_info(void)
-{
-}
+ mask = 1 << irq;
+ if (level)
+ fs->regs[R_R_NMI] |= mask;
+ else
+ fs->regs[R_R_NMI] &= ~mask;
-void irq_info(void)
-{
+ qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]);
}
-static void etraxfs_pic_handler(void *opaque, int irq, int level)
-{
- struct fs_pic_state_t *fs = (void *)opaque;
- CPUState *env = fs->env;
- int i;
- uint32_t vector = 0;
-
- D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n",
- __func__, irq, level,
- fs->rw_mask, fs->r_vect, fs->r_masked_vect));
-
- fs->r_vect &= ~(1 << irq);
- fs->r_vect |= (!!level << irq);
- fs->r_masked_vect = fs->r_vect & fs->rw_mask;
-
- /* The ETRAX interrupt controller signals interrupts to teh core
- through an interrupt request wire and an irq vector bus. If
- multiple interrupts are simultaneously active it chooses vector
- 0x30 and lets the sw choose the priorities. */
- if (fs->r_masked_vect) {
- uint32_t mv = fs->r_masked_vect;
- for (i = 0; i < 31; i++) {
- if (mv & 1) {
- vector = 0x31 + i;
- /* Check for multiple interrupts. */
- if (mv > 1)
- vector = 0x30;
- break;
- }
- mv >>= 1;
- }
- if (vector) {
- env->interrupt_vector = vector;
- D(printf("%s vector=%x\n", __func__, vector));
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- }
- } else {
- env->interrupt_vector = 0;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
- D(printf("%s reset irqs\n", __func__));
- }
+static void irq_handler(void *opaque, int irq, int level)
+{
+ struct etrax_pic *fs = (void *)opaque;
+
+ if (irq >= 30)
+ return nmi_handler(opaque, irq, level);
+
+ irq -= 1;
+ fs->regs[R_R_VECT] &= ~(1 << irq);
+ fs->regs[R_R_VECT] |= (!!level << irq);
+ pic_update(fs);
}
-qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
+static int etraxfs_pic_init(SysBusDevice *dev)
{
- struct fs_pic_state_t *fs;
- qemu_irq *pic;
- int intr_vect_regs;
+ struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev);
+
+ qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
+ sysbus_init_irq(dev, &s->parent_irq);
+ sysbus_init_irq(dev, &s->parent_nmi);
+
+ memory_region_init_io(&s->mmio, &pic_ops, s, "etraxfs-pic", R_MAX * 4);
+ sysbus_init_mmio(dev, &s->mmio);
+ return 0;
+}
+
+static Property etraxfs_pic_properties[] = {
+ DEFINE_PROP_PTR("interrupt_vector", struct etrax_pic, interrupt_vector),
+ DEFINE_PROP_END_OF_LIST(),
+};
- fs = qemu_mallocz(sizeof *fs);
- if (!fs)
- return NULL;
- fs->env = env;
+static void etraxfs_pic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- pic = qemu_allocate_irqs(etraxfs_pic_handler, fs, 30);
+ k->init = etraxfs_pic_init;
+ dc->props = etraxfs_pic_properties;
+}
- intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
- cpu_register_physical_memory(base, 0x14, intr_vect_regs);
- fs->base = base;
+static TypeInfo etraxfs_pic_info = {
+ .name = "etraxfs,pic",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct etrax_pic),
+ .class_init = etraxfs_pic_class_init,
+};
- return pic;
+static void etraxfs_pic_register_types(void)
+{
+ type_register_static(&etraxfs_pic_info);
}
+
+type_init(etraxfs_pic_register_types)
projects / qemu.git / blobdiff