target/ppc: Remove "compat" property of server class POWER CPUs

[qemu.git] / disas / ppc.c

diff --git a/disas/ppc.c b/disas/ppc.c
index 052cebe8514dea3f54b26b42a02a2244a18fd08b..02be8781983270f1ce05d766d6a76e82d90bf700 100644 (file)
--- a/disas/ppc.c
+++ b/disas/ppc.c
@@ -19,7 +19,7 @@ You should have received a copy of the GNU General Public License
 along with this file; see the file COPYING.  If not,
 see <http://www.gnu.org/licenses/>.  */
 #include "qemu/osdep.h"
-#include "disas/bfd.h"
+#include "disas/dis-asm.h"
 #define BFD_DEFAULT_TARGET_SIZE 64
 
 /* ppc.h -- Header file for PowerPC opcode table
@@ -1653,11 +1653,11 @@ extract_tbr (unsigned long insn,
 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
 
-/* An Context form instruction.  */
+/* A Context form instruction.  */
 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
 #define CTX_MASK CTX(0x3f, 0x7)
 
-/* An User Context form instruction.  */
+/* A User Context form instruction.  */
 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
 #define UCTX_MASK UCTX(0x3f, 0x1f)
 
@@ -1710,19 +1710,19 @@ extract_tbr (unsigned long insn,
 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 
-/* An VX form instruction.  */
+/* A VX form instruction.  */
 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
 
 /* The mask for an VX form instruction.  */
 #define VX_MASK        VX(0x3f, 0x7ff)
 
-/* An VA form instruction.  */
+/* A VA form instruction.  */
 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
 
-/* The mask for an VA form instruction.  */
+/* The mask for a VA form instruction.  */
 #define VXA_MASK VXA(0x3f, 0x3f)
 
-/* An VXR form instruction.  */
+/* A VXR form instruction.  */
 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
 
 /* The mask for a VXR form instruction.  */
@@ -1765,6 +1765,9 @@ extract_tbr (unsigned long insn,
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 
+/* An X form instruction with the RA field fixed.  */
+#define XRA(op, xop, ra) (X((op), (xop)) | (((ra) << 16) & XRA_MASK))
+
 /* An XRARB_MASK, but with the L bit clear.  */
 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
 
@@ -1955,6 +1958,9 @@ extract_tbr (unsigned long insn,
 #define POWER4 PPC_OPCODE_POWER4
 #define POWER5 PPC_OPCODE_POWER5
 #define POWER6 PPC_OPCODE_POWER6
+/* Documentation purposes only; we don't actually check the isa for disas.  */
+#define POWER7  PPC_OPCODE_POWER6
+#define POWER9  PPC_OPCODE_POWER6
 #define CELL   PPC_OPCODE_CELL
 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
@@ -2286,6 +2292,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "vrlh",      VX(4,   68), VX_MASK,   PPCVEC,         { VD, VA, VB } },
 { "vrlw",      VX(4,  132), VX_MASK,   PPCVEC,         { VD, VA, VB } },
 { "vrsqrtefp", VX(4,  330), VX_MASK,   PPCVEC,         { VD, VB } },
+{ "vrldmi",    VX(4,  197), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vrldnm",    VX(4,  453), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vrlwmi",    VX(4,  133), VX_MASK,    PPCVEC,         { VD, VA, VB} },
+{ "vrlwnm",    VX(4,  389), VX_MASK,    PPCVEC,         { VD, VA, VB } },
 { "vsel",      VXA(4,  42), VXA_MASK,  PPCVEC,         { VD, VA, VB, VC } },
 { "vsl",       VX(4,  452), VX_MASK,   PPCVEC,         { VD, VA, VB } },
 { "vslb",      VX(4,  260), VX_MASK,   PPCVEC,         { VD, VA, VB } },
@@ -3585,6 +3595,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "lbzux",   X(31,119),        X_MASK,         COM,            { RT, RAL, RB } },
 
 { "popcntb", X(31,122), XRB_MASK,      POWER5,         { RA, RS } },
+{ "popcntw", X(31,378), XRB_MASK,       POWER7,         { RA, RS } },
+{ "popcntd", X(31,506), XRB_MASK,       POWER7,         { RA, RS } },
+
+{ "cnttzw",  XRC(31,538,0), XRB_MASK,   POWER9,         { RA, RS } },
+{ "cnttzw.", XRC(31,538,1), XRB_MASK,   POWER9,         { RA, RS } },
+{ "cnttzd",  XRC(31,570,0), XRB_MASK,   POWER9,         { RA, RS } },
+{ "cnttzd.", XRC(31,570,1), XRB_MASK,   POWER9,         { RA, RS } },
 
 { "not",     XRC(31,124,0), X_MASK,    COM,            { RA, RS, RBS } },
 { "nor",     XRC(31,124,0), X_MASK,    COM,            { RA, RS, RB } },
@@ -3720,6 +3737,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,                { RT, RA } },
 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,                { RT, RA } },
 
+{ "addex",   XO(31,170,0,0), XO_MASK,   POWER9,         { RT, RA, RB } },
+
 { "mullw",   XO(31,235,0,0), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "muls",    XO(31,235,0,0), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 { "mullw.",  XO(31,235,0,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
@@ -4982,6 +5001,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "ddivq",   XRC(63,546,0), X_MASK,    POWER6,         { FRT, FRA, FRB } },
 { "ddivq.",  XRC(63,546,1), X_MASK,    POWER6,         { FRT, FRA, FRB } },
 
+{ "mffsl",   XRA(63,583,12), XRARB_MASK,       POWER9, { FRT } },
+
 { "mffs",    XRC(63,583,0), XRARB_MASK,        COM,            { FRT } },
 { "mffs.",   XRC(63,583,1), XRARB_MASK,        COM,            { FRT } },
 
@@ -5205,7 +5226,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,
       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
        {
          /* BITM is always some number of zeros followed by some
-            number of ones, followed by some numer of zeros.  */
+            number of ones, followed by some number of zeros.  */
          unsigned long top = operand->bitm;
          /* top & -top gives the rightmost 1 bit, so this
             fills in any trailing zeros.  */