#include "boards.h"
#include "qemu-log.h"
#include "loader.h"
+#include "blockdev.h"
+#include "exec-memory.h"
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2048 * 1024)
ref405ep_fpga_t *fpga;
int fpga_memory;
- fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
+ fpga = g_malloc0(sizeof(ref405ep_fpga_t));
fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
- ref405ep_fpga_write, fpga);
+ ref405ep_fpga_write, fpga,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
- ref405ep_fpga_reset(fpga);
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
ppc4xx_bd_info_t bd;
CPUPPCState *env;
qemu_irq *pic;
- ram_addr_t sram_offset, bios_offset, bdloc;
+ MemoryRegion *bios;
+ ram_addr_t sram_offset, bdloc;
+ MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
- target_ulong sram_size, bios_size;
+ target_ulong sram_size;
+ long bios_size;
//int phy_addr = 0;
//static int phy_addr = 1;
- target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
+ target_ulong kernel_base, initrd_base;
+ long kernel_size, initrd_size;
int linux_boot;
int fl_idx, fl_sectors, len;
- int ppc_boot_device = boot_device[0];
DriveInfo *dinfo;
/* XXX: fix this */
- ram_bases[0] = qemu_ram_alloc(0x08000000);
+ memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x08000000;
+ memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
ram_size = 128 * 1024 * 1024;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
sram_size = 512 * 1024;
- sram_offset = qemu_ram_alloc(sram_size);
+ sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
#ifdef DEBUG_BOARD_INIT
printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
#endif
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) {
bios_size = bdrv_getlength(dinfo->bdrv);
- bios_offset = qemu_ram_alloc(bios_size);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " TARGET_FMT_lx
- " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
+ printf("Register parallel flash %d size %lx"
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
+ pflash_cfi02_register((uint32_t)(-bios_size),
+ NULL, "ef405ep.bios", bios_size,
dinfo->bdrv, 65536, fl_sectors, 1,
- 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
+ 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
+ 1);
fl_idx++;
} else
#endif
#ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n");
#endif
- bios_offset = qemu_ram_alloc(BIOS_SIZE);
+ bios = g_new(MemoryRegion, 1);
+ memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
- bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
- qemu_free(filename);
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
+ g_free(filename);
} else {
bios_size = -1;
}
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(get_system_memory(),
+ (uint32_t)(-bios_size), bios);
}
/* Register FPGA */
#ifdef DEBUG_BOARD_INIT
kernel_filename);
exit(1);
}
- printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
+ printf("Load kernel size %ld at " TARGET_FMT_lx,
kernel_size, kernel_base);
/* load initrd */
if (initrd_filename) {
}
env->gpr[4] = initrd_base;
env->gpr[5] = initrd_size;
- ppc_boot_device = 'm';
if (kernel_cmdline != NULL) {
len = strlen(kernel_cmdline);
bdloc -= ((len + 255) & ~255);
taihu_cpld_t *cpld;
int cpld_memory;
- cpld = qemu_mallocz(sizeof(taihu_cpld_t));
+ cpld = g_malloc0(sizeof(taihu_cpld_t));
cpld_memory = cpu_register_io_memory(taihu_cpld_read,
- taihu_cpld_write, cpld);
+ taihu_cpld_write, cpld,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
- taihu_cpld_reset(cpld);
qemu_register_reset(&taihu_cpld_reset, cpld);
}
const char *cpu_model)
{
char *filename;
- CPUPPCState *env;
qemu_irq *pic;
- ram_addr_t bios_offset;
+ MemoryRegion *bios;
+ MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
- target_ulong bios_size;
- target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
+ long bios_size;
+ target_ulong kernel_base, initrd_base;
+ long kernel_size, initrd_size;
int linux_boot;
int fl_idx, fl_sectors;
- int ppc_boot_device = boot_device[0];
DriveInfo *dinfo;
/* RAM is soldered to the board so the size cannot be changed */
- ram_bases[0] = qemu_ram_alloc(0x04000000);
+ memory_region_init_ram(&ram_memories[0], NULL,
+ "taihu_405ep.ram-0", 0x04000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x04000000;
- ram_bases[1] = qemu_ram_alloc(0x04000000);
+ memory_region_init_ram(&ram_memories[1], NULL,
+ "taihu_405ep.ram-1", 0x04000000);
+ ram_bases[1] = 0x04000000;
ram_sizes[1] = 0x04000000;
ram_size = 0x08000000;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
- kernel_filename == NULL ? 0 : 1);
+ ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
+ kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
printf("%s: register BIOS\n", __func__);
/* XXX: should check that size is 2MB */
// bios_size = 2 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
- bios_offset = qemu_ram_alloc(bios_size);
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " TARGET_FMT_lx
- " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
+ printf("Register parallel flash %d size %lx"
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
+ pflash_cfi02_register((uint32_t)(-bios_size),
+ NULL, "taihu_405ep.bios", bios_size,
dinfo->bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
+ 1);
fl_idx++;
} else
#endif
#endif
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
- bios_offset = qemu_ram_alloc(BIOS_SIZE);
+ bios = g_new(MemoryRegion, 1);
+ memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
- bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
+ g_free(filename);
} else {
bios_size = -1;
}
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(get_system_memory(), (uint32_t)(-bios_size),
+ bios);
}
/* Register Linux flash */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
bios_size = 32 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " TARGET_FMT_lx
- " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
- fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
+ printf("Register parallel flash %d size %lx"
+ " at addr " TARGET_FMT_lx " '%s'\n",
+ fl_idx, bios_size, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv));
#endif
- bios_offset = qemu_ram_alloc(bios_size);
- pflash_cfi02_register(0xfc000000, bios_offset,
+ pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
dinfo->bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
+ 1);
fl_idx++;
}
/* Register CLPD & LCD display */
initrd_base = 0;
initrd_size = 0;
}
- ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
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