Revert last change, this workaround is long obsolete.

[qemu.git] / exec-all.h

diff --git a/exec-all.h b/exec-all.h
index 380300698751d29652c8822989492494caa07f57..dbfe457614f66632b06d2bdfe5885c0a2c962486 100644 (file)
--- a/exec-all.h
+++ b/exec-all.h
@@ -62,6 +62,7 @@ extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
 extern target_ulong gen_opc_jump_pc[2];
 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
 extern target_ulong gen_opc_jump_pc[2];

+extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

 
 typedef void (GenOpFunc)(void);
 typedef void (GenOpFunc1)(long);
 
 typedef void (GenOpFunc)(void);
 typedef void (GenOpFunc1)(long);


@@ -77,6 +78,9 @@ void optimize_flags_init(void);
 extern FILE *logfile;
 extern int loglevel;
 
 extern FILE *logfile;
 extern int loglevel;
 

+void muls64(int64_t *phigh, int64_t *plow, int64_t a, int64_t b);
+void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
+

 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);


@@ -91,23 +95,28 @@ int cpu_restore_state_copy(struct TranslationBlock *tb,
                            CPUState *env, unsigned long searched_pc,
                            void *puc);
 void cpu_resume_from_signal(CPUState *env1, void *puc);
                            CPUState *env, unsigned long searched_pc,
                            void *puc);
 void cpu_resume_from_signal(CPUState *env1, void *puc);

-void cpu_exec_init(void);
-int page_unprotect(unsigned long address, unsigned long pc, void *puc);
+void cpu_exec_init(CPUState *env);
+int page_unprotect(target_ulong address, unsigned long pc, void *puc);

 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                    int is_cpu_write_access);
 void tb_invalidate_page_range(target_ulong start, target_ulong end);
 void tlb_flush_page(CPUState *env, target_ulong addr);
 void tlb_flush(CPUState *env, int flush_global);
 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                    int is_cpu_write_access);
 void tb_invalidate_page_range(target_ulong start, target_ulong end);
 void tlb_flush_page(CPUState *env, target_ulong addr);
 void tlb_flush(CPUState *env, int flush_global);

-int tlb_set_page(CPUState *env, target_ulong vaddr, 
-                 target_phys_addr_t paddr, int prot, 
-                 int is_user, int is_softmmu);
+int tlb_set_page_exec(CPUState *env, target_ulong vaddr, 
+                      target_phys_addr_t paddr, int prot, 
+                      int is_user, int is_softmmu);
+static inline int tlb_set_page(CPUState *env, target_ulong vaddr, 
+                               target_phys_addr_t paddr, int prot, 
+                               int is_user, int is_softmmu)
+{
+    if (prot & PAGE_READ)
+        prot |= PAGE_EXEC;
+    return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
+}

 
 #define CODE_GEN_MAX_SIZE        65536
 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 
 
 #define CODE_GEN_MAX_SIZE        65536
 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 

-#define CODE_GEN_HASH_BITS     15
-#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)
-

 #define CODE_GEN_PHYS_HASH_BITS     15
 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 
 #define CODE_GEN_PHYS_HASH_BITS     15
 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 


@@ -167,7 +176,6 @@ typedef struct TranslationBlock {
 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 
     uint8_t *tc_ptr;    /* pointer to the translated code */
 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 
     uint8_t *tc_ptr;    /* pointer to the translated code */

-    struct TranslationBlock *hash_next; /* next matching tb for virtual address */

     /* next matching tb for physical address. */
     struct TranslationBlock *phys_hash_next; 
     /* first and second physical page containing code. The lower bit
     /* next matching tb for physical address. */
     struct TranslationBlock *phys_hash_next; 
     /* first and second physical page containing code. The lower bit


@@ -191,9 +199,19 @@ typedef struct TranslationBlock {
     struct TranslationBlock *jmp_first;
 } TranslationBlock;
 
     struct TranslationBlock *jmp_first;
 } TranslationBlock;
 

-static inline unsigned int tb_hash_func(target_ulong pc)
+static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)

 {
 {

-    return pc & (CODE_GEN_HASH_SIZE - 1);
+    target_ulong tmp;
+    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
+    return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
+}
+
+static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
+{
+    target_ulong tmp;
+    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
+    return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
+           (tmp & TB_JMP_ADDR_MASK));

 }
 
 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 }
 
 static inline unsigned int tb_phys_hash_func(unsigned long pc)


@@ -203,41 +221,14 @@ static inline unsigned int tb_phys_hash_func(unsigned long pc)
 
 TranslationBlock *tb_alloc(target_ulong pc);
 void tb_flush(CPUState *env);
 
 TranslationBlock *tb_alloc(target_ulong pc);
 void tb_flush(CPUState *env);

-void tb_link(TranslationBlock *tb);

 void tb_link_phys(TranslationBlock *tb, 
                   target_ulong phys_pc, target_ulong phys_page2);
 
 void tb_link_phys(TranslationBlock *tb, 
                   target_ulong phys_pc, target_ulong phys_page2);
 

-extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];

 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 
 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 extern uint8_t *code_gen_ptr;
 
 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 
 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 extern uint8_t *code_gen_ptr;
 

-/* find a translation block in the translation cache. If not found,
-   return NULL and the pointer to the last element of the list in pptb */
-static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
-                                        target_ulong pc, 
-                                        target_ulong cs_base,
-                                        unsigned int flags)
-{
-    TranslationBlock **ptb, *tb;
-    unsigned int h;
- 
-    h = tb_hash_func(pc);
-    ptb = &tb_hash[h];
-    for(;;) {
-        tb = *ptb;
-        if (!tb)
-            break;
-        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
-            return tb;
-        ptb = &tb->hash_next;
-    }
-    *pptb = ptb;
-    return NULL;
-}
-
-

 #if defined(USE_DIRECT_JUMP)
 
 #if defined(__powerpc__)
 #if defined(USE_DIRECT_JUMP)
 
 #if defined(__powerpc__)


@@ -369,7 +360,7 @@ extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 
 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 

-#ifdef __powerpc__
+#if defined(__powerpc__)

 static inline int testandset (int *p)
 {
     int ret;
 static inline int testandset (int *p)
 {
     int ret;


@@ -385,9 +376,7 @@ static inline int testandset (int *p)
                           : "cr0", "memory");
     return ret;
 }
                           : "cr0", "memory");
     return ret;
 }

-#endif
-
-#ifdef __i386__
+#elif defined(__i386__)

 static inline int testandset (int *p)
 {
     long int readval = 0;
 static inline int testandset (int *p)
 {
     long int readval = 0;


@@ -398,9 +387,7 @@ static inline int testandset (int *p)
                           : "cc");
     return readval;
 }
                           : "cc");
     return readval;
 }

-#endif
-
-#ifdef __x86_64__
+#elif defined(__x86_64__)

 static inline int testandset (int *p)
 {
     long int readval = 0;
 static inline int testandset (int *p)
 {
     long int readval = 0;


@@ -411,9 +398,7 @@ static inline int testandset (int *p)
                           : "cc");
     return readval;
 }
                           : "cc");
     return readval;
 }

-#endif
-
-#ifdef __s390__
+#elif defined(__s390__)

 static inline int testandset (int *p)
 {
     int ret;
 static inline int testandset (int *p)
 {
     int ret;


@@ -425,9 +410,7 @@ static inline int testandset (int *p)
                          : "cc", "memory" );
     return ret;
 }
                          : "cc", "memory" );
     return ret;
 }

-#endif
-
-#ifdef __alpha__
+#elif defined(__alpha__)

 static inline int testandset (int *p)
 {
     int ret;
 static inline int testandset (int *p)
 {
     int ret;


@@ -444,9 +427,7 @@ static inline int testandset (int *p)
                          : "m" (*p));
     return ret;
 }
                          : "m" (*p));
     return ret;
 }

-#endif
-
-#ifdef __sparc__
+#elif defined(__sparc__)

 static inline int testandset (int *p)
 {
        int ret;
 static inline int testandset (int *p)
 {
        int ret;


@@ -458,9 +439,7 @@ static inline int testandset (int *p)
 
        return (ret ? 1 : 0);
 }
 
        return (ret ? 1 : 0);
 }

-#endif
-
-#ifdef __arm__
+#elif defined(__arm__)

 static inline int testandset (int *spinlock)
 {
     register unsigned int ret;
 static inline int testandset (int *spinlock)
 {
     register unsigned int ret;


@@ -470,9 +449,7 @@ static inline int testandset (int *spinlock)
     
     return ret;
 }
     
     return ret;
 }

-#endif
-
-#ifdef __mc68000
+#elif defined(__mc68000)

 static inline int testandset (int *p)
 {
     char ret;
 static inline int testandset (int *p)
 {
     char ret;


@@ -482,15 +459,36 @@ static inline int testandset (int *p)
                          : "cc","memory");
     return ret;
 }
                          : "cc","memory");
     return ret;
 }

-#endif
+#elif defined(__ia64)

 
 

-#ifdef __ia64

 #include <ia64intrin.h>
 
 static inline int testandset (int *p)
 {
     return __sync_lock_test_and_set (p, 1);
 }
 #include <ia64intrin.h>
 
 static inline int testandset (int *p)
 {
     return __sync_lock_test_and_set (p, 1);
 }

+#elif defined(__mips__)
+static inline int testandset (int *p)
+{
+    int ret;
+
+    __asm__ __volatile__ (
+       "       .set push               \n"
+       "       .set noat               \n"
+       "       .set mips2              \n"
+       "1:     li      $1, 1           \n"
+       "       ll      %0, %1          \n"
+       "       sc      $1, %1          \n"
+       "       beqz    $1, 1b          \n"
+       "       .set pop                "
+       : "=r" (ret), "+R" (*p)
+       :
+       : "memory");
+
+    return ret;
+}
+#else
+#error unimplemented CPU support

 #endif
 
 typedef int spinlock_t;
 #endif
 
 typedef int spinlock_t;


@@ -580,38 +578,55 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
     is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
 #elif defined (TARGET_SPARC)
     is_user = (env->psrs == 0);
     is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
 #elif defined (TARGET_SPARC)
     is_user = (env->psrs == 0);

+#elif defined (TARGET_ARM)
+    is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
+#elif defined (TARGET_SH4)
+    is_user = ((env->sr & SR_MD) == 0);
+#elif defined (TARGET_ALPHA)
+    is_user = ((env->ps >> 3) & 3);
+#elif defined (TARGET_M68K)
+    is_user = ((env->sr & SR_S) == 0);

 #else
 #else

-#error "Unimplemented !"
+#error unimplemented CPU

 #endif
 #endif

-    if (__builtin_expect(env->tlb_read[is_user][index].address != 
+    if (__builtin_expect(env->tlb_table[is_user][index].addr_code != 

                          (addr & TARGET_PAGE_MASK), 0)) {
         ldub_code(addr);
     }
                          (addr & TARGET_PAGE_MASK), 0)) {
         ldub_code(addr);
     }

-    pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
-    if (pd > IO_MEM_ROM) {
-        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
+    pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
+    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
+#ifdef TARGET_SPARC
+        do_unassigned_access(addr, 0, 1, 0);
+#else
+        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
+#endif

     }
     }

-    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
+    return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;

 }
 #endif
 
 }
 #endif
 

-

 #ifdef USE_KQEMU
 #ifdef USE_KQEMU

+#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
+

 int kqemu_init(CPUState *env);
 int kqemu_cpu_exec(CPUState *env);
 void kqemu_flush_page(CPUState *env, target_ulong addr);
 void kqemu_flush(CPUState *env, int global);
 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 int kqemu_init(CPUState *env);
 int kqemu_cpu_exec(CPUState *env);
 void kqemu_flush_page(CPUState *env, target_ulong addr);
 void kqemu_flush(CPUState *env, int global);
 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);

+void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);

 void kqemu_cpu_interrupt(CPUState *env);
 void kqemu_cpu_interrupt(CPUState *env);

+void kqemu_record_dump(void);

 
 static inline int kqemu_is_ok(CPUState *env)
 {
     return(env->kqemu_enabled &&
 
 static inline int kqemu_is_ok(CPUState *env)
 {
     return(env->kqemu_enabled &&

-           (env->hflags & HF_CPL_MASK) == 3 &&
-           (env->eflags & IOPL_MASK) != IOPL_MASK &&

            (env->cr[0] & CR0_PE_MASK) && 
            (env->cr[0] & CR0_PE_MASK) && 

+           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&

            (env->eflags & IF_MASK) &&
            (env->eflags & IF_MASK) &&

-           !(env->eflags & VM_MASK));
+           !(env->eflags & VM_MASK) &&
+           (env->kqemu_enabled == 2 || 
+            ((env->hflags & HF_CPL_MASK) == 3 &&
+             (env->eflags & IOPL_MASK) != IOPL_MASK)));

 }
 
 #endif
 }
 
 #endif