if (do_exp && env->exception_index != 0x1e0) {
env->exception_index = 0x000; /* masked exception -> reset */
}
- if (do_irq) {
+ if (do_irq && !env->intr_at_halt) {
return; /* masked */
}
+ env->intr_at_halt = 0;
}
if (do_irq) {
env->sgr = env->gregs[15];
env->sr |= SR_BL | SR_MD | SR_RB;
+ if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
+ /* Branch instruction should be executed again before delay slot. */
+ env->spc -= 2;
+ /* Clear flags for exception/interrupt routine. */
+ env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
+ }
+ if (env->flags & DELAY_SLOT_CLEARME)
+ env->flags = 0;
+
if (do_exp) {
env->expevt = env->exception_index;
switch (env->exception_index) {
switch (itlbnb) {
case 0:
- and_mask = 0x7f;
+ and_mask = 0x1f;
break;
case 1:
and_mask = 0xe7;
break;
}
- env->mmucr &= (and_mask << 24);
+ env->mmucr &= (and_mask << 24) | 0x00ffffff;
env->mmucr |= (or_mask << 24);
}
{
if ((env->mmucr & 0xe0000000) == 0xe0000000)
return 0;
- if ((env->mmucr & 0x98000000) == 0x08000000)
+ if ((env->mmucr & 0x98000000) == 0x18000000)
return 1;
if ((env->mmucr & 0x54000000) == 0x04000000)
return 2;
for (i = 0; i < nbtlb; i++) {
if (!entries[i].v)
continue; /* Invalid entry */
- if (use_asid && entries[i].asid != asid && !entries[i].sh)
+ if (use_asid && entries[i].asid != asid)
continue; /* Bad ASID */
#if 0
switch (entries[i].sz) {
start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
end = start + entries[i].size - 1;
if (address >= start && address <= end) { /* Match */
- if (match != -1)
+ if (match != MMU_DTLB_MISS)
return MMU_DTLB_MULTIPLE; /* Multiple match */
match = i;
}
return match;
}
+static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
+ const tlb_t * needle)
+{
+ int i;
+ for (i = 0; i < nbtlb; i++)
+ if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
+ return 1;
+ return 0;
+}
+
+static void increment_urc(CPUState * env)
+{
+ uint8_t urb, urc;
+
+ /* Increment URC */
+ urb = ((env->mmucr) >> 18) & 0x3f;
+ urc = ((env->mmucr) >> 10) & 0x3f;
+ urc++;
+ if (urc == urb || urc == UTLB_SIZE - 1)
+ urc = 0;
+ env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
+}
+
/* Find itlb entry - update itlb from utlb if necessary and asked for
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
Update the itlb from utlb if update is not 0
else if (e == MMU_DTLB_MISS && update) {
e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
if (e >= 0) {
+ tlb_t * ientry;
n = itlb_replacement(env);
- env->itlb[n] = env->utlb[e];
+ ientry = &env->itlb[n];
+ if (ientry->v) {
+ if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
+ tlb_flush_page(env, ientry->vpn << 10);
+ }
+ *ientry = env->utlb[e];
e = n;
- }
- }
+ } else if (e == MMU_DTLB_MISS)
+ e = MMU_ITLB_MISS;
+ } else if (e == MMU_DTLB_MISS)
+ e = MMU_ITLB_MISS;
if (e >= 0)
update_itlb_use(env, e);
return e;
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
- uint8_t urb, urc;
-
- /* Increment URC */
- urb = ((env->mmucr) >> 18) & 0x3f;
- urc = ((env->mmucr) >> 10) & 0x3f;
- urc++;
- if (urc == urb || urc == UTLB_SIZE - 1)
- urc = 0;
- env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
+ /* per utlb access */
+ increment_urc(env);
/* Return entry */
return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
int use_asid, is_code, n;
tlb_t *matching = NULL;
- use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
+ use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
is_code = env->pc == address; /* Hack */
/* Use a hack to find if this is an instruction or data access */
return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
MMU_DTLB_MISS_READ;
}
- /* Mask upper 3 bits */
- *physical = address & 0x1FFFFFFF;
+ if (address >= 0x80000000 && address < 0xc0000000) {
+ /* Mask upper 3 bits for P1 and P2 areas */
+ *physical = address & 0x1fffffff;
+ } else if (address >= 0xfc000000) {
+ /*
+ * Mask upper 3 bits for control registers in P4 area,
+ * to unify access to control registers via P0-P3 area.
+ * The addresses for cache store queue, TLB address array
+ * are not masked.
+ */
+ *physical = address & 0x1fffffff;
+ } else {
+ /* access to cache store queue, or TLB address array. */
+ *physical = address;
+ }
*prot = PAGE_READ | PAGE_WRITE;
return MMU_OK;
}
target_ulong physical, page_offset, page_size;
int prot, ret, access_type;
+ switch (rw) {
+ case 0:
+ rw = PAGE_READ;
+ break;
+ case 1:
+ rw = PAGE_WRITE;
+ break;
+ case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
+ rw = PAGE_READ;
+ break;
+ default:
+ /* fatal error */
+ assert(0);
+ }
+
/* XXXXX */
#if 0
fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
return physical;
}
+void cpu_load_tlb(CPUState * env)
+{
+ int n = cpu_mmucr_urc(env->mmucr);
+ tlb_t * entry = &env->utlb[n];
+
+ if (entry->v) {
+ /* Overwriting valid entry in utlb. */
+ target_ulong address = entry->vpn << 10;
+ if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
+ tlb_flush_page(env, address);
+ }
+ }
+
+ /* per utlb access cannot implemented. */
+ increment_urc(env);
+
+ /* Take values into cpu status from registers. */
+ entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
+ entry->vpn = cpu_pteh_vpn(env->pteh);
+ entry->v = (uint8_t)cpu_ptel_v(env->ptel);
+ entry->ppn = cpu_ptel_ppn(env->ptel);
+ entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
+ switch (entry->sz) {
+ case 0: /* 00 */
+ entry->size = 1024; /* 1K */
+ break;
+ case 1: /* 01 */
+ entry->size = 1024 * 4; /* 4K */
+ break;
+ case 2: /* 10 */
+ entry->size = 1024 * 64; /* 64K */
+ break;
+ case 3: /* 11 */
+ entry->size = 1024 * 1024; /* 1M */
+ break;
+ default:
+ assert(0);
+ break;
+ }
+ entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
+ entry->c = (uint8_t)cpu_ptel_c(env->ptel);
+ entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
+ entry->d = (uint8_t)cpu_ptel_d(env->ptel);
+ entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
+ entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
+ entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
+}
+
+void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+ uint32_t mem_value)
+{
+ int associate = addr & 0x0000080;
+ uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
+ uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
+ uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
+ uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
+
+ if (associate) {
+ int i;
+ tlb_t * utlb_match_entry = NULL;
+ int needs_tlb_flush = 0;
+
+ /* search UTLB */
+ for (i = 0; i < UTLB_SIZE; i++) {
+ tlb_t * entry = &s->utlb[i];
+ if (!entry->v)
+ continue;
+
+ if (entry->vpn == vpn && entry->asid == asid) {
+ if (utlb_match_entry) {
+ /* Multiple TLB Exception */
+ s->exception_index = 0x140;
+ s->tea = addr;
+ break;
+ }
+ if (entry->v && !v)
+ needs_tlb_flush = 1;
+ entry->v = v;
+ entry->d = d;
+ utlb_match_entry = entry;
+ }
+ increment_urc(s); /* per utlb access */
+ }
+
+ /* search ITLB */
+ for (i = 0; i < ITLB_SIZE; i++) {
+ tlb_t * entry = &s->itlb[i];
+ if (entry->vpn == vpn && entry->asid == asid) {
+ if (entry->v && !v)
+ needs_tlb_flush = 1;
+ if (utlb_match_entry)
+ *entry = *utlb_match_entry;
+ else
+ entry->v = v;
+ break;
+ }
+ }
+
+ if (needs_tlb_flush)
+ tlb_flush_page(s, vpn << 10);
+
+ } else {
+ int index = (addr & 0x00003f00) >> 8;
+ tlb_t * entry = &s->utlb[index];
+ if (entry->v) {
+ /* Overwriting valid entry in utlb. */
+ target_ulong address = entry->vpn << 10;
+ if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
+ tlb_flush_page(s, address);
+ }
+ }
+ entry->asid = asid;
+ entry->vpn = vpn;
+ entry->d = d;
+ entry->v = v;
+ increment_urc(s);
+ }
+}
+
#endif
projects / qemu.git / blobdiff