Merge remote-tracking branch 'qemu-kvm/memory/core' into staging

[qemu.git] / hw / realview_gic.c

diff --git a/hw/realview_gic.c b/hw/realview_gic.c
index bd02b095e838009c0ab85cc9dc0ae7da3f7c0dc5..071ef13c9e2dac2cf2d5ee1c37457306ccf213aa 100644 (file)
--- a/hw/realview_gic.c
+++ b/hw/realview_gic.c
@@ -4,12 +4,11 @@
  * Copyright (c) 2006-2007 CodeSourcery.
  * Written by Paul Brook
  *
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
  */
 
 #include "sysbus.h"
 
-#define GIC_NIRQ 96
 #define NCPU 1
 
 /* Only a single "CPU" interface is present.  */
@@ -23,56 +22,47 @@ gic_get_current_cpu(void)
 
 typedef struct {
     gic_state gic;
-    int iomemtype;
+    MemoryRegion container;
 } RealViewGICState;
 
-static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
+static void realview_gic_map_setup(RealViewGICState *s)
 {
-    gic_state *s = (gic_state *)opaque;
-    return gic_cpu_read(s, gic_get_current_cpu(), offset);
+    memory_region_init(&s->container, "realview-gic-container", 0x2000);
+    memory_region_add_subregion(&s->container, 0, &s->gic.cpuiomem[0]);
+    memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
 }
 
-static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
-                          uint32_t value)
-{
-    gic_state *s = (gic_state *)opaque;
-    gic_cpu_write(s, gic_get_current_cpu(), offset, value);
-}
-
-static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = {
-   realview_gic_cpu_read,
-   realview_gic_cpu_read,
-   realview_gic_cpu_read
-};
-
-static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = {
-   realview_gic_cpu_write,
-   realview_gic_cpu_write,
-   realview_gic_cpu_write
-};
-
-static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base)
+static int realview_gic_init(SysBusDevice *dev)
 {
     RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
-    cpu_register_physical_memory(base, 0x1000, s->iomemtype);
-    cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+
+    /* The GICs on the RealView boards have a fixed nonconfigurable
+     * number of interrupt lines, so we don't need to expose this as
+     * a qdev property.
+     */
+    gic_init(&s->gic, 96);
+    realview_gic_map_setup(s);
+    sysbus_init_mmio(dev, &s->container);
+    return 0;
 }
 
-static int realview_gic_init(SysBusDevice *dev)
+static void realview_gic_class_init(ObjectClass *klass, void *data)
 {
-    RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
+    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 
-    gic_init(&s->gic);
-    s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
-                                          realview_gic_cpu_writefn, s);
-    sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
-    return 0;
+    sdc->init = realview_gic_init;
 }
 
-static void realview_gic_register_devices(void)
+static TypeInfo realview_gic_info = {
+    .name          = "realview_gic",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(RealViewGICState),
+    .class_init    = realview_gic_class_init,
+};
+
+static void realview_gic_register_types(void)
 {
-    sysbus_register_dev("realview_gic", sizeof(RealViewGICState),
-                        realview_gic_init);
+    type_register_static(&realview_gic_info);
 }
 
-device_init(realview_gic_register_devices)
+type_init(realview_gic_register_types)