* Copyright (c) 2006 Openedhand Ltd.
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GNU GPL v2.
*/
#ifndef PXA_H
# define PXA_H "pxa.h"
+#include "memory.h"
+
/* Interrupt numbers */
# define PXA2XX_PIC_SSP3 0
# define PXA2XX_PIC_USBH2 2
# define PXA2XX_PIC_USBH1 3
+# define PXA2XX_PIC_KEYPAD 4
# define PXA2XX_PIC_PWRI2C 6
# define PXA25X_PIC_HWUART 7
# define PXA27X_PIC_OST_4_11 7
# define PXA2XX_RX_RQ_SSP3 66
# define PXA2XX_TX_RQ_SSP3 67
-# define PXA2XX_RAM_BASE 0xa0000000
+# define PXA2XX_SDRAM_BASE 0xa0000000
+# define PXA2XX_INTERNAL_BASE 0x5c000000
+# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-struct pxa2xx_pic_state_s;
-qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
+DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
/* pxa2xx_gpio.c */
-struct pxa2xx_gpio_info_s;
-struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
- CPUState *env, qemu_irq *pic, int lines);
-void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level);
-void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
- gpio_handler_t handler, void *opaque);
-void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
- void (*handler)(void *opaque), void *opaque);
+DeviceState *pxa2xx_gpio_init(hwaddr base,
+ CPUARMState *env, DeviceState *pic, int lines);
+void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
-struct pxa2xx_dma_state_s;
-struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
- qemu_irq irq);
-struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
- qemu_irq irq);
-void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
+DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
+DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
+
+/* pxa2xx_lcd.c */
+typedef struct PXA2xxLCDState PXA2xxLCDState;
+PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
+ hwaddr base, qemu_irq irq);
+void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
+void pxa2xx_lcdc_oritentation(void *opaque, int angle);
+
+/* pxa2xx_mmci.c */
+typedef struct PXA2xxMMCIState PXA2xxMMCIState;
+PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
+ hwaddr base,
+ BlockDriverState *bd, qemu_irq irq,
+ qemu_irq rx_dma, qemu_irq tx_dma);
+void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
+ qemu_irq coverswitch);
+
+/* pxa2xx_pcmcia.c */
+typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
+PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
+ hwaddr base);
+int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
+int pxa2xx_pcmcia_dettach(void *opaque);
+void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
+
+/* pxa2xx_keypad.c */
+struct keymap {
+ int column;
+ int row;
+};
+typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
+PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
+ hwaddr base,
+ qemu_irq irq);
+void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
+ int size);
/* pxa2xx.c */
-struct pxa2xx_ssp_s;
-void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
- uint32_t (*readfn)(void *opaque),
- void (*writefn)(void *opaque, uint32_t value), void *opaque);
-
-struct pxa2xx_i2s_s;
-struct pxa2xx_fir_s;
-
-struct pxa2xx_state_s {
- CPUState *env;
- qemu_irq *pic;
- struct pxa2xx_dma_state_s *dma;
- struct pxa2xx_gpio_info_s *gpio;
- struct pxa2xx_ssp_s **ssp;
- struct pxa2xx_i2s_s *i2s;
- struct pxa2xx_fir_s *fir;
+typedef struct PXA2xxI2CState PXA2xxI2CState;
+PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
+ qemu_irq irq, uint32_t page_size);
+i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
+
+typedef struct PXA2xxI2SState PXA2xxI2SState;
+typedef struct PXA2xxFIrState PXA2xxFIrState;
+
+typedef struct {
+ ARMCPU *cpu;
+ DeviceState *pic;
+ qemu_irq reset;
+ MemoryRegion sdram;
+ MemoryRegion internal;
+ MemoryRegion cm_iomem;
+ MemoryRegion mm_iomem;
+ MemoryRegion pm_iomem;
+ DeviceState *dma;
+ DeviceState *gpio;
+ PXA2xxLCDState *lcd;
+ SSIBus **ssp;
+ PXA2xxI2CState *i2c[2];
+ PXA2xxMMCIState *mmc;
+ PXA2xxPCMCIAState *pcmcia[2];
+ PXA2xxI2SState *i2s;
+ PXA2xxFIrState *fir;
+ PXA2xxKeyPadState *kp;
/* Power management */
- target_phys_addr_t pm_base;
+ hwaddr pm_base;
uint32_t pm_regs[0x40];
/* Clock management */
- target_phys_addr_t cm_base;
+ hwaddr cm_base;
uint32_t cm_regs[4];
uint32_t clkcfg;
/* Memory management */
- target_phys_addr_t mm_base;
+ hwaddr mm_base;
uint32_t mm_regs[0x1a];
/* Performance monitoring */
uint32_t pmnc;
+} PXA2xxState;
- /* Real-Time clock */
- target_phys_addr_t rtc_base;
- uint32_t rttr;
- uint32_t rtsr;
- uint32_t rtar;
- uint32_t rdar1;
- uint32_t rdar2;
- uint32_t ryar1;
- uint32_t ryar2;
- uint32_t swar1;
- uint32_t swar2;
- uint32_t piar;
- uint32_t last_rcnr;
- uint32_t last_rdcr;
- uint32_t last_rycr;
- uint32_t last_swcr;
- uint32_t last_rtcpicr;
- int64_t last_hz;
- int64_t last_sw;
- int64_t last_pi;
- QEMUTimer *rtc_hz;
- QEMUTimer *rtc_rdal1;
- QEMUTimer *rtc_rdal2;
- QEMUTimer *rtc_swal1;
- QEMUTimer *rtc_swal2;
- QEMUTimer *rtc_pi;
-};
-
-struct pxa2xx_i2s_s {
- target_phys_addr_t base;
+struct PXA2xxI2SState {
+ MemoryRegion iomem;
qemu_irq irq;
- struct pxa2xx_dma_state_s *dma;
+ qemu_irq rx_dma;
+ qemu_irq tx_dma;
void (*data_req)(void *, int, int);
uint32_t control[2];
};
# define PA_FMT "0x%08lx"
-# define REG_FMT "0x%lx"
-
-struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision);
-struct pxa2xx_state_s *pxa255_init(DisplayState *ds);
+# define REG_FMT "0x" TARGET_FMT_plx
-void pxa2xx_reset(int line, int level, void *opaque);
+PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
+ const char *revision);
+PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
#endif /* PXA_H */
projects / qemu.git / blobdiff