General
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- Unimplemented ASEs:
- - MIPS16
- MDMX
- SmartMIPS
- - DSP r1
- - DSP r2
+ - microMIPS DSP r1 & r2 encodings
- MT ASE only partially implemented and not functional
- Shadow register support only partially implemented,
lacks set switching on interrupt/exception.
Existing documentation is x86-centric.
- Reverse endianness bit not implemented
- The TLB emulation is very inefficient:
- Qemu's softmmu implements a x86-style MMU, with separate entries
+ QEMU's softmmu implements a x86-style MMU, with separate entries
for read/write/execute, a TLB index which is just a modulo of the
virtual address, and a set of TLBs for each user/kernel/supervisor
MMU mode.
up to 256 ASID tags as additional matching criterion (which roughly
equates to 256 MMU modes). It also has a global flag which causes
entries to match regardless of ASID.
- To cope with these differences, Qemu currently flushes the TLB at
+ To cope with these differences, QEMU currently flushes the TLB at
each ASID change. Using the MMU modes to implement ASIDs hinges on
implementing the global bit efficiently.
- save/restore of the CPU state is not implemented (see machine.c).
"Generic" 4Kc system emulation
------------------------------
-- Doesn't correspond to any real hardware.
+- Doesn't correspond to any real hardware. Should be removed some day,
+ U-Boot is the last remaining user.
PICA 61 system emulation
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MALTA system emulation
----------------------
- We fake firmware support instead of doing the real thing
-- Real firmware falls over when trying to init RAM, presumably due
- to lacking system controller emulation.
+- Real firmware (YAMON) falls over when trying to init RAM, presumably
+ due to lacking system controller emulation.
- Bonito system controller not implemented
- MSC1 system controller not implemented