#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "target/mips/trace.h"
#include "trace-tcg.h"
#include "exec/translator.h"
#include "exec/log.h"
+#include "qemu/qemu-print.h"
#define MIPS_DEBUG_DISAS 0
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget, bcond;
+static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
#endif
#undef OP_LD_ATOMIC
-#ifdef CONFIG_USER_ONLY
-#define OP_ST_ATOMIC(insn,fname,ldname,almask) \
-static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, int mem_idx, \
- DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_temp_new(); \
- TCGLabel *l1 = gen_new_label(); \
- TCGLabel *l2 = gen_new_label(); \
- \
- tcg_gen_andi_tl(t0, arg2, almask); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
- tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); \
- generate_exception(ctx, EXCP_AdES); \
- gen_set_label(l1); \
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
- tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
- tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \
- tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \
- generate_exception_end(ctx, EXCP_SC); \
- gen_set_label(l2); \
- tcg_gen_movi_tl(t0, 0); \
- gen_store_gpr(t0, rt); \
- tcg_temp_free(t0); \
-}
-#else
-#define OP_ST_ATOMIC(insn,fname,ldname,almask) \
-static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, int mem_idx, \
- DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_temp_new(); \
- gen_helper_1e2i(insn, t0, arg1, arg2, mem_idx); \
- gen_store_gpr(t0, rt); \
- tcg_temp_free(t0); \
-}
-#endif
-OP_ST_ATOMIC(sc,st32,ld32s,0x3);
-#if defined(TARGET_MIPS64)
-OP_ST_ATOMIC(scd,st64,ld64,0x7);
-#endif
-#undef OP_ST_ATOMIC
-
static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
int base, int offset)
{
/* Store conditional */
-static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
- int base, int16_t offset)
+static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
+ TCGMemOp tcg_mo, bool eva)
{
- TCGv t0, t1;
- int mem_idx = ctx->mem_idx;
+ TCGv addr, t0, val;
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *done = gen_new_label();
-#ifdef CONFIG_USER_ONLY
- t0 = tcg_temp_local_new();
- t1 = tcg_temp_local_new();
-#else
t0 = tcg_temp_new();
- t1 = tcg_temp_new();
-#endif
- gen_base_offset_addr(ctx, t0, base, offset);
- gen_load_gpr(t1, rt);
- switch (opc) {
-#if defined(TARGET_MIPS64)
- case OPC_SCD:
- case R6_OPC_SCD:
- op_st_scd(t1, t0, rt, mem_idx, ctx);
- break;
-#endif
- case OPC_SCE:
- mem_idx = MIPS_HFLAG_UM;
- /* fall through */
- case OPC_SC:
- case R6_OPC_SC:
- op_st_sc(t1, t0, rt, mem_idx, ctx);
- break;
- }
- tcg_temp_free(t1);
+ addr = tcg_temp_new();
+ /* compare the address against that of the preceeding LL */
+ gen_base_offset_addr(ctx, addr, base, offset);
+ tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
+ tcg_temp_free(addr);
+ tcg_gen_movi_tl(t0, 0);
+ gen_store_gpr(t0, rt);
+ tcg_gen_br(done);
+
+ gen_set_label(l1);
+ /* generate cmpxchg */
+ val = tcg_temp_new();
+ gen_load_gpr(val, rt);
+ tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val,
+ eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo);
+ tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval);
+ gen_store_gpr(t0, rt);
+ tcg_temp_free(val);
+
+ gen_set_label(done);
tcg_temp_free(t0);
}
+
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
- uint32_t reg1, uint32_t reg2)
+ uint32_t reg1, uint32_t reg2, bool eva)
{
TCGv taddr = tcg_temp_local_new();
TCGv lladdr = tcg_temp_local_new();
tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
- ctx->mem_idx, MO_64);
+ eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
if (reg1 != 0) {
tcg_gen_movi_tl(cpu_gpr[reg1], 1);
}
tcg_temp_free(t1);
}
+#if defined(TARGET_MIPS64)
/* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
break;
}
}
+#endif
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
tcg_temp_free(t1);
}
+#if defined(TARGET_MIPS64)
static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
{
TCGv t0, t1;
tcg_temp_free(t0);
tcg_temp_free(t1);
}
+#endif
static void gen_muldiv(DisasContext *ctx, uint32_t opc,
int acc, int rs, int rt)
case CP0_REGISTER_17:
switch (sel) {
case 0:
- gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr),
+ gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
#endif
}
+#ifdef CONFIG_USER_ONLY
+/* The above should dead-code away any calls to this..*/
+static inline void gen_helper_do_semihosting(void *env)
+{
+ g_assert_not_reached();
+}
+#endif
+
static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
{
int rx, ry;
gen_st(ctx, mips32_op, rt, rs, offset);
break;
case SC:
- gen_st_cond(ctx, OPC_SC, rt, rs, offset);
+ gen_st_cond(ctx, rt, rs, offset, MO_TESL, false);
break;
#if defined(TARGET_MIPS64)
case SCD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- gen_st_cond(ctx, OPC_SCD, rt, rs, offset);
+ gen_st_cond(ctx, rt, rs, offset, MO_TEQ, false);
break;
#endif
case LD_EVA:
mips32_op = OPC_SHE;
goto do_st_lr;
case SCE:
- gen_st_cond(ctx, OPC_SCE, rt, rs, offset);
+ gen_st_cond(ctx, rt, rs, offset, MO_TESL, true);
break;
case SWE:
mips32_op = OPC_SWE;
/* extraction utilities */
-#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
-#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
-#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
+#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
+#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
+#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
{
- int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
- int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
switch (extract32(ctx->opcode, 2, 2)) {
case NM_NOT16:
goto out;
}
+ /* branch completion */
+ clear_branch_hflags(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
if (bcond_compute == 0) {
/* Uncoditional compact branch */
gen_goto_tb(ctx, 0, ctx->btarget);
tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
gen_op_addr_add(ctx, btarget, t1, t0);
+ /* branch completion */
+ clear_branch_hflags(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
/* unconditional branch to register */
tcg_gen_mov_tl(cpu_PC, btarget);
tcg_gen_lookup_and_goto_ptr();
goto out;
}
+ /* branch completion */
+ clear_branch_hflags(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
/* Generating branch here as compact branches don't have delay slot */
gen_goto_tb(ctx, 1, ctx->btarget);
gen_set_label(fs);
case NM_P_SC:
switch (ctx->opcode & 0x03) {
case NM_SC:
- gen_st_cond(ctx, OPC_SC, rt, rs, s);
+ gen_st_cond(ctx, rt, rs, s, MO_TESL, false);
break;
case NM_SCWP:
check_xnp(ctx);
- gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
+ false);
break;
}
break;
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
- gen_st_cond(ctx, OPC_SCE, rt, rs, s);
+ gen_st_cond(ctx, rt, rs, s, MO_TESL, true);
break;
case NM_SCWPE:
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
- gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
+ true);
break;
default:
generate_exception_end(ctx, EXCP_RI);
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
- int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
- int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
- int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
+ int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
int offset;
int imm;
break;
case NM_SB16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
gen_st(ctx, OPC_SB, rt, rs, offset);
break;
case NM_LBU16:
break;
case NM_SH16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
gen_st(ctx, OPC_SH, rt, rs, offset);
break;
case NM_LHU16:
break;
case NM_SW16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
- rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
+ rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
offset = extract32(ctx->opcode, 0, 4) << 2;
gen_st(ctx, OPC_SW, rt, rs, offset);
break;
case NM_SWGP16:
rt = decode_gpr_gpr3_src_store(
- NANOMIPS_EXTRACT_RD(ctx->opcode));
+ NANOMIPS_EXTRACT_RT3(ctx->opcode));
offset = extract32(ctx->opcode, 0, 7) << 2;
gen_st(ctx, OPC_SW, rt, 28, offset);
break;
}
+#if defined(TARGET_MIPS64)
+
+/*
+ *
+ * MMI (MultiMedia Interface) ASE instructions
+ * ===========================================
+ */
+
+/*
+ * MMI instructions category: data communication
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * PCPYH PEXCH PEXTLB PINTH PPACB PEXT5 PREVH
+ * PCPYLD PEXCW PEXTLH PINTEH PPACH PPAC5 PROT3W
+ * PCPYUD PEXEH PEXTLW PPACW
+ * PEXEW PEXTUB
+ * PEXTUH
+ * PEXTUW
+ */
+
+/*
+ * PCPYH rd, rt
+ *
+ * Parallel Copy Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyh(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = (1ULL << 16) - 1;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
+/*
+ * PCPYLD rd, rs, rt
+ *
+ * Parallel Copy Lower Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYLD | MMI2 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyld(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ if (rs == 0) {
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ } else {
+ if (rd != rt) {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
+ }
+ }
+ }
+}
+
+/*
+ * PCPYUD rd, rs, rt
+ *
+ * Parallel Copy Upper Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYUD | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyud(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ if (rs == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ if (rd != rt) {
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+ }
+ }
+ }
+}
+
+#endif
+
+
#if !defined(TARGET_MIPS64)
/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
}
break;
case R6_OPC_SC:
- gen_st_cond(ctx, op1, rt, rs, imm);
+ gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
break;
case R6_OPC_LL:
gen_ld(ctx, op1, rt, rs, imm);
break;
#if defined(TARGET_MIPS64)
case R6_OPC_SCD:
- gen_st_cond(ctx, op1, rt, rs, imm);
+ gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false);
break;
case R6_OPC_LLD:
gen_ld(ctx, op1, rt, rs, imm);
}
}
+
+#if defined(TARGET_MIPS64)
+
static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI0(ctx->opcode);
case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */
case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */
case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */
- case MMI_OPC_2_PCPYLD: /* TODO: MMI_OPC_2_PCPYLD */
case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */
case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */
case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
+ case MMI_OPC_2_PCPYLD:
+ gen_mmi_pcpyld(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
generate_exception_end(ctx, EXCP_RI);
case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */
case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
- case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
- case MMI_OPC_3_PCPYH: /* TODO: MMI_OPC_3_PCPYH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
+ case MMI_OPC_3_PCPYH:
+ gen_mmi_pcpyh(ctx);
+ break;
+ case MMI_OPC_3_PCPYUD:
+ gen_mmi_pcpyud(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
gen_mmi_sq(ctx, base, rt, offset);
}
+#endif
+
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
return;
case OPC_SCE:
check_cp0_enabled(ctx);
- gen_st_cond(ctx, op1, rt, rs, imm);
+ gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
return;
case OPC_CACHEE:
check_cp0_enabled(ctx);
generate_exception_end(ctx, EXCP_RI);
break;
}
+ if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
+ (df == DF_WORD)) {
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_COPY_U_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_WORD:
+ gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_INSERT_df:
- gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
break;
}
break;
decode_opc_special(env, ctx);
break;
case OPC_SPECIAL2:
+#if defined(TARGET_MIPS64)
if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_mmi(env, ctx);
-#if !defined(TARGET_MIPS64)
- } else if (ctx->insn_flags & ASE_MXU) {
+#else
+ if (ctx->insn_flags & ASE_MXU) {
decode_opc_mxu(env, ctx);
#endif
} else {
}
break;
case OPC_SPECIAL3:
+#if defined(TARGET_MIPS64)
if (ctx->insn_flags & INSN_R5900) {
decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
} else {
decode_opc_special3(env, ctx);
}
+#else
+ decode_opc_special3(env, ctx);
+#endif
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- gen_st_cond(ctx, op, rt, rs, imm);
- break;
+ gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
+ break;
case OPC_CACHE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cp0_enabled(ctx);
check_insn_opc_user_only(ctx, INSN_R5900);
}
check_mips_64(ctx);
- gen_st_cond(ctx, op, rt, rs, imm);
+ gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS32R6) {
break;
case OPC_MSA: /* OPC_MDMX */
if (ctx->insn_flags & INSN_R5900) {
+#if defined(TARGET_MIPS64)
gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
+#endif
} else {
/* MDMX: Not implemented. */
gen_msa(env, ctx);
.disas_log = mips_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
DisasContext ctx;
- translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
+ translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
}
-static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
- int flags)
+static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
{
int i;
int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
#define printfpr(fp) \
do { \
if (is_fpu64) \
- fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
- " fd:%13g fs:%13g psu: %13g\n", \
- (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
- (double)(fp)->fd, \
- (double)(fp)->fs[FP_ENDIAN_IDX], \
- (double)(fp)->fs[!FP_ENDIAN_IDX]); \
+ qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
+ " fd:%13g fs:%13g psu: %13g\n", \
+ (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
+ (double)(fp)->fd, \
+ (double)(fp)->fs[FP_ENDIAN_IDX], \
+ (double)(fp)->fs[!FP_ENDIAN_IDX]); \
else { \
fpr_t tmp; \
tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
- fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
- " fd:%13g fs:%13g psu:%13g\n", \
- tmp.w[FP_ENDIAN_IDX], tmp.d, \
- (double)tmp.fd, \
- (double)tmp.fs[FP_ENDIAN_IDX], \
- (double)tmp.fs[!FP_ENDIAN_IDX]); \
+ qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
+ " fd:%13g fs:%13g psu:%13g\n", \
+ tmp.w[FP_ENDIAN_IDX], tmp.d, \
+ (double)tmp.fd, \
+ (double)tmp.fs[FP_ENDIAN_IDX], \
+ (double)tmp.fs[!FP_ENDIAN_IDX]); \
} \
} while(0)
- fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
- env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
- get_float_exception_flags(&env->active_fpu.fp_status));
+ qemu_fprintf(f,
+ "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
+ get_float_exception_flags(&env->active_fpu.fp_status));
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
- fpu_fprintf(f, "%3s: ", fregnames[i]);
+ qemu_fprintf(f, "%3s: ", fregnames[i]);
printfpr(&env->active_fpu.fpr[i]);
}
#undef printfpr
}
-void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
int i;
- cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
- " LO=0x" TARGET_FMT_lx " ds %04x "
- TARGET_FMT_lx " " TARGET_FMT_ld "\n",
- env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
- env->hflags, env->btarget, env->bcond);
+ qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
+ " LO=0x" TARGET_FMT_lx " ds %04x "
+ TARGET_FMT_lx " " TARGET_FMT_ld "\n",
+ env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
+ env->hflags, env->btarget, env->bcond);
for (i = 0; i < 32; i++) {
if ((i & 3) == 0)
- cpu_fprintf(f, "GPR%02d:", i);
- cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);
+ qemu_fprintf(f, "GPR%02d:", i);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx,
+ regnames[i], env->active_tc.gpr[i]);
if ((i & 3) == 3)
- cpu_fprintf(f, "\n");
- }
-
- cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
- env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
- cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
- PRIx64 "\n",
- env->CP0_Config0, env->CP0_Config1, env->lladdr);
- cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
- env->CP0_Config2, env->CP0_Config3);
- cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
- env->CP0_Config4, env->CP0_Config5);
+ qemu_fprintf(f, "\n");
+ }
+
+ qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
+ env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
+ qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
+ PRIx64 "\n",
+ env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
+ qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
+ env->CP0_Config2, env->CP0_Config3);
+ qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
+ env->CP0_Config4, env->CP0_Config5);
if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
- fpu_dump_state(env, f, cpu_fprintf, flags);
+ fpu_dump_state(env, f, flags);
}
}
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
+ cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr),
+ "lladdr");
+ cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
+ "llval");
#if defined(TARGET_MIPS64)
cpu_mmr[0] = NULL;
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
-bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
+bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
{
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->insn_flags & isa) != 0;
void cpu_state_reset(CPUMIPSState *env)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
projects / qemu.git / blobdiff