xilinx_spips: Inhibit interrupts in LQSPI mode

[qemu.git] / target-openrisc / cpu.c

diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index e23100fa0986a1a44908521f5c24f196f170ddbd..ffe14f3c8dcc00e023bd0ff98fefd00ac36c99a1 100644 (file)
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -62,19 +62,24 @@ static inline void set_feature(OpenRISCCPU *cpu, int feature)
     cpu->env.cpucfgr = cpu->feature;
 }
 
     cpu->env.cpucfgr = cpu->feature;
 }
 

-void openrisc_cpu_realize(Object *obj, Error **errp)
+static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)

 {
 {

-    OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+    OpenRISCCPU *cpu = OPENRISC_CPU(dev);
+    OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);

 
     qemu_init_vcpu(&cpu->env);
     cpu_reset(CPU(cpu));
 
     qemu_init_vcpu(&cpu->env);
     cpu_reset(CPU(cpu));

+
+    occ->parent_realize(dev, errp);

 }
 
 static void openrisc_cpu_initfn(Object *obj)
 {
 }
 
 static void openrisc_cpu_initfn(Object *obj)
 {

+    CPUState *cs = CPU(obj);

     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
     static int inited;
 
     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
     static int inited;
 

+    cs->env_ptr = &cpu->env;

     cpu_exec_init(&cpu->env);
 
 #ifndef CONFIG_USER_ONLY
     cpu_exec_init(&cpu->env);
 
 #ifndef CONFIG_USER_ONLY


@@ -98,7 +103,8 @@ static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
     }
 
     oc = object_class_by_name(cpu_model);
     }
 
     oc = object_class_by_name(cpu_model);

-    if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU)) {
+    if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
+                       object_class_is_abstract(oc))) {

         return NULL;
     }
     return oc;
         return NULL;
     }
     return oc;


@@ -133,24 +139,30 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 {
     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(occ);
 {
     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
     CPUClass *cc = CPU_CLASS(occ);

+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    occ->parent_realize = dc->realize;
+    dc->realize = openrisc_cpu_realizefn;

 
     occ->parent_reset = cc->reset;
     cc->reset = openrisc_cpu_reset;
 
     cc->class_by_name = openrisc_cpu_class_by_name;
 
     occ->parent_reset = cc->reset;
     cc->reset = openrisc_cpu_reset;
 
     cc->class_by_name = openrisc_cpu_class_by_name;

+    cc->do_interrupt = openrisc_cpu_do_interrupt;

 }
 
 static void cpu_register(const OpenRISCCPUInfo *info)
 {
     TypeInfo type_info = {
 }
 
 static void cpu_register(const OpenRISCCPUInfo *info)
 {
     TypeInfo type_info = {

-        .name = info->name,

         .parent = TYPE_OPENRISC_CPU,
         .instance_size = sizeof(OpenRISCCPU),
         .instance_init = info->initfn,
         .class_size = sizeof(OpenRISCCPUClass),
     };
 
         .parent = TYPE_OPENRISC_CPU,
         .instance_size = sizeof(OpenRISCCPU),
         .instance_init = info->initfn,
         .class_size = sizeof(OpenRISCCPUClass),
     };
 

-    type_register_static(&type_info);
+    type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
+    type_register(&type_info);
+    g_free((void *)type_info.name);

 }
 
 static const TypeInfo openrisc_cpu_type_info = {
 }
 
 static const TypeInfo openrisc_cpu_type_info = {


@@ -158,7 +170,7 @@ static const TypeInfo openrisc_cpu_type_info = {
     .parent = TYPE_CPU,
     .instance_size = sizeof(OpenRISCCPU),
     .instance_init = openrisc_cpu_initfn,
     .parent = TYPE_CPU,
     .instance_size = sizeof(OpenRISCCPU),
     .instance_init = openrisc_cpu_initfn,

-    .abstract = false,
+    .abstract = true,

     .class_size = sizeof(OpenRISCCPUClass),
     .class_init = openrisc_cpu_class_init,
 };
     .class_size = sizeof(OpenRISCCPUClass),
     .class_init = openrisc_cpu_class_init,
 };


@@ -185,7 +197,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
     cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
     cpu->env.cpu_model_str = cpu_model;
 
     cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
     cpu->env.cpu_model_str = cpu_model;
 

-    openrisc_cpu_realize(OBJECT(cpu), NULL);
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);

 
     return cpu;
 }
 
     return cpu;
 }


@@ -199,9 +211,9 @@ static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 
     name_a = object_class_get_name(class_a);
     name_b = object_class_get_name(class_b);
 
     name_a = object_class_get_name(class_a);
     name_b = object_class_get_name(class_b);

-    if (strcmp(name_a, "any") == 0) {
+    if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {

         return 1;
         return 1;

-    } else if (strcmp(name_b, "any") == 0) {
+    } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {

         return -1;
     } else {
         return strcmp(name_a, name_b);
         return -1;
     } else {
         return strcmp(name_a, name_b);


@@ -212,9 +224,15 @@ static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 {
     ObjectClass *oc = data;
     CPUListState *s = user_data;
 {
     ObjectClass *oc = data;
     CPUListState *s = user_data;

+    const char *typename;
+    char *name;

 
 

+    typename = object_class_get_name(oc);
+    name = g_strndup(typename,
+                     strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));

     (*s->cpu_fprintf)(s->file, "  %s\n",
     (*s->cpu_fprintf)(s->file, "  %s\n",

-                      object_class_get_name(oc));
+                      name);
+    g_free(name);

 }
 
 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 }
 
 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)