target/riscv: rationalise softfloat includes

[qemu.git] / stubs / trace-control.c

diff --git a/stubs/trace-control.c b/stubs/trace-control.c
index f765a02018890c8df5996232ce9b6dcead23fc4c..7f856e5c24e34d41e87872308050b4584c955cab 100644 (file)
--- a/stubs/trace-control.c
+++ b/stubs/trace-control.c
@@ -18,22 +18,21 @@ void trace_event_set_state_dynamic_init(TraceEvent *ev, bool state)
 
 void trace_event_set_state_dynamic(TraceEvent *ev, bool state)
 {
-    TraceEventID id;
     bool state_pre;
     assert(trace_event_get_state_static(ev));
-    id = trace_event_get_id(ev);
+
     /*
      * We ignore the "vcpu" property here, since there's no target code. Then
      * dstate can only be 1 or 0.
      */
-    state_pre = trace_events_dstate[id];
+    state_pre = *(ev->dstate);
     if (state_pre != state) {
         if (state) {
             trace_events_enabled_count++;
-            trace_events_dstate[id] = 1;
+            *(ev->dstate) = 1;
         } else {
             trace_events_enabled_count--;
-            trace_events_dstate[id] = 0;
+            *(ev->dstate) = 0;
         }
     }
 }