Add 'static' to please Sparse

[qemu.git] / target-mips / op_helper.c

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index dcadd031ed606c6c28433d1956b54db777a1b776..d3dab33a36a99abae781ce6abb84c028837ce756 100644 (file)
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -14,34 +14,34 @@
  * Lesser General Public License for more details.
  *
  * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 #include <stdlib.h>
 #include "exec.h"
 
 #include "host-utils.h"
 
+#include "helper.h"
 /*****************************************************************************/
 /* Exceptions processing helpers */
 
-void do_raise_exception_err (uint32_t exception, int error_code)
+void helper_raise_exception_err (uint32_t exception, int error_code)
 {
 #if 1
-    if (logfile && exception < 0x100)
-        fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
+    if (exception < 0x100)
+        qemu_log("%s: %d %d\n", __func__, exception, error_code);
 #endif
     env->exception_index = exception;
     env->error_code = error_code;
     cpu_loop_exit();
 }
 
-void do_raise_exception (uint32_t exception)
+void helper_raise_exception (uint32_t exception)
 {
-    do_raise_exception_err(exception, 0);
+    helper_raise_exception_err(exception, 0);
 }
 
-void do_interrupt_restart (void)
+void helper_interrupt_restart (void)
 {
     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
         !(env->CP0_Status & (1 << CP0St_ERL)) &&
@@ -49,11 +49,12 @@ void do_interrupt_restart (void)
         (env->CP0_Status & (1 << CP0St_IE)) &&
         (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
         env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
-        do_raise_exception(EXCP_EXT_INTERRUPT);
+        helper_raise_exception(EXCP_EXT_INTERRUPT);
     }
 }
 
-void do_restore_state (void *pc_ptr)
+#if !defined(CONFIG_USER_ONLY)
+static void do_restore_state (void *pc_ptr)
 {
     TranslationBlock *tb;
     unsigned long pc = (unsigned long) pc_ptr;
@@ -63,26 +64,27 @@ void do_restore_state (void *pc_ptr)
         cpu_restore_state (tb, env, pc, NULL);
     }
 }
+#endif
 
-target_ulong do_clo (target_ulong t0)
+target_ulong helper_clo (target_ulong arg1)
 {
-    return clo32(t0);
+    return clo32(arg1);
 }
 
-target_ulong do_clz (target_ulong t0)
+target_ulong helper_clz (target_ulong arg1)
 {
-    return clz32(t0);
+    return clz32(arg1);
 }
 
 #if defined(TARGET_MIPS64)
-target_ulong do_dclo (target_ulong t0)
+target_ulong helper_dclo (target_ulong arg1)
 {
-    return clo64(t0);
+    return clo64(arg1);
 }
 
-target_ulong do_dclz (target_ulong t0)
+target_ulong helper_dclz (target_ulong arg1)
 {
-    return clz64(t0);
+    return clz64(arg1);
 }
 #endif /* TARGET_MIPS64 */
 
@@ -98,160 +100,126 @@ static inline void set_HILO (uint64_t HILO)
     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 }
 
-static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
+static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
 {
     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
-    t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
+    arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 }
 
-static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
+static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
 {
-    t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
+    arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 }
 
-#if TARGET_LONG_BITS > HOST_LONG_BITS
-void do_madd (target_ulong t0, target_ulong t1)
-{
-    int64_t tmp;
-
-    tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
-    set_HILO((int64_t)get_HILO() + tmp);
-}
-
-void do_maddu (target_ulong t0, target_ulong t1)
-{
-    uint64_t tmp;
-
-    tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
-    set_HILO(get_HILO() + tmp);
-}
-
-void do_msub (target_ulong t0, target_ulong t1)
-{
-    int64_t tmp;
-
-    tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
-    set_HILO((int64_t)get_HILO() - tmp);
-}
-
-void do_msubu (target_ulong t0, target_ulong t1)
-{
-    uint64_t tmp;
-
-    tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
-    set_HILO(get_HILO() - tmp);
-}
-#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
-
 /* Multiplication variants of the vr54xx. */
-target_ulong do_muls (target_ulong t0, target_ulong t1)
+target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_mulsu (target_ulong t0, target_ulong t1)
+target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_macc (target_ulong t0, target_ulong t1)
+target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_macchi (target_ulong t0, target_ulong t1)
+target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_maccu (target_ulong t0, target_ulong t1)
+target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_macchiu (target_ulong t0, target_ulong t1)
+target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_msac (target_ulong t0, target_ulong t1)
+target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_msachi (target_ulong t0, target_ulong t1)
+target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_msacu (target_ulong t0, target_ulong t1)
+target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_msachiu (target_ulong t0, target_ulong t1)
+target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_mulhi (target_ulong t0, target_ulong t1)
+target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
+    set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
+target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
+    set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_mulshi (target_ulong t0, target_ulong t1)
+target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
+target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
 #ifdef TARGET_MIPS64
-void do_dmult (target_ulong t0, target_ulong t1)
+void helper_dmult (target_ulong arg1, target_ulong arg2)
 {
-    muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
+    muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 }
 
-void do_dmultu (target_ulong t0, target_ulong t1)
+void helper_dmultu (target_ulong arg1, target_ulong arg2)
 {
-    mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
+    mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 }
 #endif
 
@@ -263,7 +231,7 @@ void do_dmultu (target_ulong t0, target_ulong t1)
 #define GET_OFFSET(addr, offset) (addr - (offset))
 #endif
 
-target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     target_ulong tmp;
 
@@ -280,27 +248,27 @@ target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 
-    if (GET_LMASK(t0) <= 2) {
-        tmp = ldfun(GET_OFFSET(t0, 1));
-        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
+    if (GET_LMASK(arg2) <= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, 1));
+        arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
     }
 
-    if (GET_LMASK(t0) <= 1) {
-        tmp = ldfun(GET_OFFSET(t0, 2));
-        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
+    if (GET_LMASK(arg2) <= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, 2));
+        arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
     }
 
-    if (GET_LMASK(t0) == 0) {
-        tmp = ldfun(GET_OFFSET(t0, 3));
-        t1 = (t1 & 0xFFFFFF00) | tmp;
+    if (GET_LMASK(arg2) == 0) {
+        tmp = ldfun(GET_OFFSET(arg2, 3));
+        arg1 = (arg1 & 0xFFFFFF00) | tmp;
     }
-    return (int32_t)t1;
+    return (int32_t)arg1;
 }
 
-target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     target_ulong tmp;
 
@@ -317,27 +285,27 @@ target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0xFFFFFF00) | tmp;
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0xFFFFFF00) | tmp;
 
-    if (GET_LMASK(t0) >= 1) {
-        tmp = ldfun(GET_OFFSET(t0, -1));
-        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
+    if (GET_LMASK(arg2) >= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, -1));
+        arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
     }
 
-    if (GET_LMASK(t0) >= 2) {
-        tmp = ldfun(GET_OFFSET(t0, -2));
-        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
+    if (GET_LMASK(arg2) >= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, -2));
+        arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
     }
 
-    if (GET_LMASK(t0) == 3) {
-        tmp = ldfun(GET_OFFSET(t0, -3));
-        t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
+    if (GET_LMASK(arg2) == 3) {
+        tmp = ldfun(GET_OFFSET(arg2, -3));
+        arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
     }
-    return (int32_t)t1;
+    return (int32_t)arg1;
 }
 
-void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -352,19 +320,19 @@ void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)(t1 >> 24));
+    stfun(arg2, (uint8_t)(arg1 >> 24));
 
-    if (GET_LMASK(t0) <= 2)
-        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
+    if (GET_LMASK(arg2) <= 2)
+        stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK(t0) <= 1)
-        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
+    if (GET_LMASK(arg2) <= 1)
+        stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK(t0) == 0)
-        stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
+    if (GET_LMASK(arg2) == 0)
+        stfun(GET_OFFSET(arg2, 3), (uint8_t)arg1);
 }
 
-void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -379,16 +347,16 @@ void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)t1);
+    stfun(arg2, (uint8_t)arg1);
 
-    if (GET_LMASK(t0) >= 1)
-        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
+    if (GET_LMASK(arg2) >= 1)
+        stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK(t0) >= 2)
-        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
+    if (GET_LMASK(arg2) >= 2)
+        stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK(t0) == 3)
-        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
+    if (GET_LMASK(arg2) == 3)
+        stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
 }
 
 #if defined(TARGET_MIPS64)
@@ -401,7 +369,7 @@ void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 #endif
 
-target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     uint64_t tmp;
 
@@ -418,48 +386,48 @@ target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 
-    if (GET_LMASK64(t0) <= 6) {
-        tmp = ldfun(GET_OFFSET(t0, 1));
-        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
+    if (GET_LMASK64(arg2) <= 6) {
+        tmp = ldfun(GET_OFFSET(arg2, 1));
+        arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
     }
 
-    if (GET_LMASK64(t0) <= 5) {
-        tmp = ldfun(GET_OFFSET(t0, 2));
-        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
+    if (GET_LMASK64(arg2) <= 5) {
+        tmp = ldfun(GET_OFFSET(arg2, 2));
+        arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
     }
 
-    if (GET_LMASK64(t0) <= 4) {
-        tmp = ldfun(GET_OFFSET(t0, 3));
-        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
+    if (GET_LMASK64(arg2) <= 4) {
+        tmp = ldfun(GET_OFFSET(arg2, 3));
+        arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
     }
 
-    if (GET_LMASK64(t0) <= 3) {
-        tmp = ldfun(GET_OFFSET(t0, 4));
-        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
+    if (GET_LMASK64(arg2) <= 3) {
+        tmp = ldfun(GET_OFFSET(arg2, 4));
+        arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
     }
 
-    if (GET_LMASK64(t0) <= 2) {
-        tmp = ldfun(GET_OFFSET(t0, 5));
-        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
+    if (GET_LMASK64(arg2) <= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, 5));
+        arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
     }
 
-    if (GET_LMASK64(t0) <= 1) {
-        tmp = ldfun(GET_OFFSET(t0, 6));
-        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
+    if (GET_LMASK64(arg2) <= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, 6));
+        arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
     }
 
-    if (GET_LMASK64(t0) == 0) {
-        tmp = ldfun(GET_OFFSET(t0, 7));
-        t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
+    if (GET_LMASK64(arg2) == 0) {
+        tmp = ldfun(GET_OFFSET(arg2, 7));
+        arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
     }
 
-    return t1;
+    return arg1;
 }
 
-target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     uint64_t tmp;
 
@@ -476,48 +444,48 @@ target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 
-    if (GET_LMASK64(t0) >= 1) {
-        tmp = ldfun(GET_OFFSET(t0, -1));
-        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
+    if (GET_LMASK64(arg2) >= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, -1));
+        arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
     }
 
-    if (GET_LMASK64(t0) >= 2) {
-        tmp = ldfun(GET_OFFSET(t0, -2));
-        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
+    if (GET_LMASK64(arg2) >= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, -2));
+        arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
     }
 
-    if (GET_LMASK64(t0) >= 3) {
-        tmp = ldfun(GET_OFFSET(t0, -3));
-        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
+    if (GET_LMASK64(arg2) >= 3) {
+        tmp = ldfun(GET_OFFSET(arg2, -3));
+        arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
     }
 
-    if (GET_LMASK64(t0) >= 4) {
-        tmp = ldfun(GET_OFFSET(t0, -4));
-        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
+    if (GET_LMASK64(arg2) >= 4) {
+        tmp = ldfun(GET_OFFSET(arg2, -4));
+        arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
     }
 
-    if (GET_LMASK64(t0) >= 5) {
-        tmp = ldfun(GET_OFFSET(t0, -5));
-        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
+    if (GET_LMASK64(arg2) >= 5) {
+        tmp = ldfun(GET_OFFSET(arg2, -5));
+        arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
     }
 
-    if (GET_LMASK64(t0) >= 6) {
-        tmp = ldfun(GET_OFFSET(t0, -6));
-        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
+    if (GET_LMASK64(arg2) >= 6) {
+        tmp = ldfun(GET_OFFSET(arg2, -6));
+        arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
     }
 
-    if (GET_LMASK64(t0) == 7) {
-        tmp = ldfun(GET_OFFSET(t0, -7));
-        t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
+    if (GET_LMASK64(arg2) == 7) {
+        tmp = ldfun(GET_OFFSET(arg2, -7));
+        arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
     }
 
-    return t1;
+    return arg1;
 }
 
-void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -532,31 +500,31 @@ void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)(t1 >> 56));
+    stfun(arg2, (uint8_t)(arg1 >> 56));
 
-    if (GET_LMASK64(t0) <= 6)
-        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
+    if (GET_LMASK64(arg2) <= 6)
+        stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48));
 
-    if (GET_LMASK64(t0) <= 5)
-        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
+    if (GET_LMASK64(arg2) <= 5)
+        stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40));
 
-    if (GET_LMASK64(t0) <= 4)
-        stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
+    if (GET_LMASK64(arg2) <= 4)
+        stfun(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32));
 
-    if (GET_LMASK64(t0) <= 3)
-        stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
+    if (GET_LMASK64(arg2) <= 3)
+        stfun(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24));
 
-    if (GET_LMASK64(t0) <= 2)
-        stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
+    if (GET_LMASK64(arg2) <= 2)
+        stfun(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK64(t0) <= 1)
-        stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
+    if (GET_LMASK64(arg2) <= 1)
+        stfun(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK64(t0) <= 0)
-        stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
+    if (GET_LMASK64(arg2) <= 0)
+        stfun(GET_OFFSET(arg2, 7), (uint8_t)arg1);
 }
 
-void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -571,59 +539,59 @@ void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)t1);
+    stfun(arg2, (uint8_t)arg1);
 
-    if (GET_LMASK64(t0) >= 1)
-        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
+    if (GET_LMASK64(arg2) >= 1)
+        stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK64(t0) >= 2)
-        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
+    if (GET_LMASK64(arg2) >= 2)
+        stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK64(t0) >= 3)
-        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
+    if (GET_LMASK64(arg2) >= 3)
+        stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
 
-    if (GET_LMASK64(t0) >= 4)
-        stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
+    if (GET_LMASK64(arg2) >= 4)
+        stfun(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32));
 
-    if (GET_LMASK64(t0) >= 5)
-        stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
+    if (GET_LMASK64(arg2) >= 5)
+        stfun(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40));
 
-    if (GET_LMASK64(t0) >= 6)
-        stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
+    if (GET_LMASK64(arg2) >= 6)
+        stfun(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48));
 
-    if (GET_LMASK64(t0) == 7)
-        stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
+    if (GET_LMASK64(arg2) == 7)
+        stfun(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56));
 }
 #endif /* TARGET_MIPS64 */
 
 #ifndef CONFIG_USER_ONLY
 /* CP0 helpers */
-target_ulong do_mfc0_mvpcontrol (void)
+target_ulong helper_mfc0_mvpcontrol (void)
 {
     return env->mvp->CP0_MVPControl;
 }
 
-target_ulong do_mfc0_mvpconf0 (void)
+target_ulong helper_mfc0_mvpconf0 (void)
 {
     return env->mvp->CP0_MVPConf0;
 }
 
-target_ulong do_mfc0_mvpconf1 (void)
+target_ulong helper_mfc0_mvpconf1 (void)
 {
     return env->mvp->CP0_MVPConf1;
 }
 
-target_ulong do_mfc0_random (void)
+target_ulong helper_mfc0_random (void)
 {
     return (int32_t)cpu_mips_get_random(env);
 }
 
-target_ulong do_mfc0_tcstatus (void)
+target_ulong helper_mfc0_tcstatus (void)
 {
     return env->active_tc.CP0_TCStatus;
 }
 
-target_ulong do_mftc0_tcstatus(void)
+target_ulong helper_mftc0_tcstatus(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -633,12 +601,12 @@ target_ulong do_mftc0_tcstatus(void)
         return env->tcs[other_tc].CP0_TCStatus;
 }
 
-target_ulong do_mfc0_tcbind (void)
+target_ulong helper_mfc0_tcbind (void)
 {
     return env->active_tc.CP0_TCBind;
 }
 
-target_ulong do_mftc0_tcbind(void)
+target_ulong helper_mftc0_tcbind(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -648,12 +616,12 @@ target_ulong do_mftc0_tcbind(void)
         return env->tcs[other_tc].CP0_TCBind;
 }
 
-target_ulong do_mfc0_tcrestart (void)
+target_ulong helper_mfc0_tcrestart (void)
 {
     return env->active_tc.PC;
 }
 
-target_ulong do_mftc0_tcrestart(void)
+target_ulong helper_mftc0_tcrestart(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -663,12 +631,12 @@ target_ulong do_mftc0_tcrestart(void)
         return env->tcs[other_tc].PC;
 }
 
-target_ulong do_mfc0_tchalt (void)
+target_ulong helper_mfc0_tchalt (void)
 {
     return env->active_tc.CP0_TCHalt;
 }
 
-target_ulong do_mftc0_tchalt(void)
+target_ulong helper_mftc0_tchalt(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -678,12 +646,12 @@ target_ulong do_mftc0_tchalt(void)
         return env->tcs[other_tc].CP0_TCHalt;
 }
 
-target_ulong do_mfc0_tccontext (void)
+target_ulong helper_mfc0_tccontext (void)
 {
     return env->active_tc.CP0_TCContext;
 }
 
-target_ulong do_mftc0_tccontext(void)
+target_ulong helper_mftc0_tccontext(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -693,12 +661,12 @@ target_ulong do_mftc0_tccontext(void)
         return env->tcs[other_tc].CP0_TCContext;
 }
 
-target_ulong do_mfc0_tcschedule (void)
+target_ulong helper_mfc0_tcschedule (void)
 {
     return env->active_tc.CP0_TCSchedule;
 }
 
-target_ulong do_mftc0_tcschedule(void)
+target_ulong helper_mftc0_tcschedule(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -708,12 +676,12 @@ target_ulong do_mftc0_tcschedule(void)
         return env->tcs[other_tc].CP0_TCSchedule;
 }
 
-target_ulong do_mfc0_tcschefback (void)
+target_ulong helper_mfc0_tcschefback (void)
 {
     return env->active_tc.CP0_TCScheFBack;
 }
 
-target_ulong do_mftc0_tcschefback(void)
+target_ulong helper_mftc0_tcschefback(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -723,12 +691,12 @@ target_ulong do_mftc0_tcschefback(void)
         return env->tcs[other_tc].CP0_TCScheFBack;
 }
 
-target_ulong do_mfc0_count (void)
+target_ulong helper_mfc0_count (void)
 {
     return (int32_t)cpu_mips_get_count(env);
 }
 
-target_ulong do_mftc0_entryhi(void)
+target_ulong helper_mftc0_entryhi(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     int32_t tcstatus;
@@ -741,7 +709,7 @@ target_ulong do_mftc0_entryhi(void)
     return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
 }
 
-target_ulong do_mftc0_status(void)
+target_ulong helper_mftc0_status(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     target_ulong t0;
@@ -760,22 +728,22 @@ target_ulong do_mftc0_status(void)
     return t0;
 }
 
-target_ulong do_mfc0_lladdr (void)
+target_ulong helper_mfc0_lladdr (void)
 {
     return (int32_t)env->CP0_LLAddr >> 4;
 }
 
-target_ulong do_mfc0_watchlo (uint32_t sel)
+target_ulong helper_mfc0_watchlo (uint32_t sel)
 {
     return (int32_t)env->CP0_WatchLo[sel];
 }
 
-target_ulong do_mfc0_watchhi (uint32_t sel)
+target_ulong helper_mfc0_watchhi (uint32_t sel)
 {
     return env->CP0_WatchHi[sel];
 }
 
-target_ulong do_mfc0_debug (void)
+target_ulong helper_mfc0_debug (void)
 {
     target_ulong t0 = env->CP0_Debug;
     if (env->hflags & MIPS_HFLAG_DM)
@@ -784,7 +752,7 @@ target_ulong do_mfc0_debug (void)
     return t0;
 }
 
-target_ulong do_mftc0_debug(void)
+target_ulong helper_mftc0_debug(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     int32_t tcstatus;
@@ -800,43 +768,43 @@ target_ulong do_mftc0_debug(void)
 }
 
 #if defined(TARGET_MIPS64)
-target_ulong do_dmfc0_tcrestart (void)
+target_ulong helper_dmfc0_tcrestart (void)
 {
     return env->active_tc.PC;
 }
 
-target_ulong do_dmfc0_tchalt (void)
+target_ulong helper_dmfc0_tchalt (void)
 {
     return env->active_tc.CP0_TCHalt;
 }
 
-target_ulong do_dmfc0_tccontext (void)
+target_ulong helper_dmfc0_tccontext (void)
 {
     return env->active_tc.CP0_TCContext;
 }
 
-target_ulong do_dmfc0_tcschedule (void)
+target_ulong helper_dmfc0_tcschedule (void)
 {
     return env->active_tc.CP0_TCSchedule;
 }
 
-target_ulong do_dmfc0_tcschefback (void)
+target_ulong helper_dmfc0_tcschefback (void)
 {
     return env->active_tc.CP0_TCScheFBack;
 }
 
-target_ulong do_dmfc0_lladdr (void)
+target_ulong helper_dmfc0_lladdr (void)
 {
     return env->CP0_LLAddr >> 4;
 }
 
-target_ulong do_dmfc0_watchlo (uint32_t sel)
+target_ulong helper_dmfc0_watchlo (uint32_t sel)
 {
     return env->CP0_WatchLo[sel];
 }
 #endif /* TARGET_MIPS64 */
 
-void do_mtc0_index (target_ulong t0)
+void helper_mtc0_index (target_ulong arg1)
 {
     int num = 1;
     unsigned int tmp = env->tlb->nb_tlb;
@@ -845,10 +813,10 @@ void do_mtc0_index (target_ulong t0)
         tmp >>= 1;
         num <<= 1;
     } while (tmp);
-    env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
+    env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 }
 
-void do_mtc0_mvpcontrol (target_ulong t0)
+void helper_mtc0_mvpcontrol (target_ulong arg1)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -858,21 +826,21 @@ void do_mtc0_mvpcontrol (target_ulong t0)
                 (1 << CP0MVPCo_EVP);
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0MVPCo_STLB);
-    newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
+    newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 
     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 
     env->mvp->CP0_MVPControl = newval;
 }
 
-void do_mtc0_vpecontrol (target_ulong t0)
+void helper_mtc0_vpecontrol (target_ulong arg1)
 {
     uint32_t mask;
     uint32_t newval;
 
     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
-    newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
+    newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 
     /* Yield scheduler intercept not implemented. */
     /* Gating storage scheduler intercept not implemented. */
@@ -882,7 +850,7 @@ void do_mtc0_vpecontrol (target_ulong t0)
     env->CP0_VPEControl = newval;
 }
 
-void do_mtc0_vpeconf0 (target_ulong t0)
+void helper_mtc0_vpeconf0 (target_ulong arg1)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -892,14 +860,14 @@ void do_mtc0_vpeconf0 (target_ulong t0)
             mask |= (0xff << CP0VPEC0_XTC);
         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
     }
-    newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
+    newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
 
     // TODO: TC exclusive handling due to ERL/EXL.
 
     env->CP0_VPEConf0 = newval;
 }
 
-void do_mtc0_vpeconf1 (target_ulong t0)
+void helper_mtc0_vpeconf1 (target_ulong arg1)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -907,7 +875,7 @@ void do_mtc0_vpeconf1 (target_ulong t0)
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                 (0xff << CP0VPEC1_NCP1);
-    newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
+    newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
 
     /* UDI not implemented. */
     /* CP2 not implemented. */
@@ -917,60 +885,60 @@ void do_mtc0_vpeconf1 (target_ulong t0)
     env->CP0_VPEConf1 = newval;
 }
 
-void do_mtc0_yqmask (target_ulong t0)
+void helper_mtc0_yqmask (target_ulong arg1)
 {
     /* Yield qualifier inputs not implemented. */
     env->CP0_YQMask = 0x00000000;
 }
 
-void do_mtc0_vpeopt (target_ulong t0)
+void helper_mtc0_vpeopt (target_ulong arg1)
 {
-    env->CP0_VPEOpt = t0 & 0x0000ffff;
+    env->CP0_VPEOpt = arg1 & 0x0000ffff;
 }
 
-void do_mtc0_entrylo0 (target_ulong t0)
+void helper_mtc0_entrylo0 (target_ulong arg1)
 {
     /* Large physaddr (PABITS) not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
+    env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
 }
 
-void do_mtc0_tcstatus (target_ulong t0)
+void helper_mtc0_tcstatus (target_ulong arg1)
 {
     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
     uint32_t newval;
 
-    newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask);
+    newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
 
     // TODO: Sync with CP0_Status.
 
     env->active_tc.CP0_TCStatus = newval;
 }
 
-void do_mttc0_tcstatus (target_ulong t0)
+void helper_mttc0_tcstatus (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     // TODO: Sync with CP0_Status.
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCStatus = t0;
+        env->active_tc.CP0_TCStatus = arg1;
     else
-        env->tcs[other_tc].CP0_TCStatus = t0;
+        env->tcs[other_tc].CP0_TCStatus = arg1;
 }
 
-void do_mtc0_tcbind (target_ulong t0)
+void helper_mtc0_tcbind (target_ulong arg1)
 {
     uint32_t mask = (1 << CP0TCBd_TBE);
     uint32_t newval;
 
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0TCBd_CurVPE);
-    newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
+    newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
     env->active_tc.CP0_TCBind = newval;
 }
 
-void do_mttc0_tcbind (target_ulong t0)
+void helper_mttc0_tcbind (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     uint32_t mask = (1 << CP0TCBd_TBE);
@@ -979,122 +947,122 @@ void do_mttc0_tcbind (target_ulong t0)
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0TCBd_CurVPE);
     if (other_tc == env->current_tc) {
-        newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
+        newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
         env->active_tc.CP0_TCBind = newval;
     } else {
-        newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask);
+        newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
         env->tcs[other_tc].CP0_TCBind = newval;
     }
 }
 
-void do_mtc0_tcrestart (target_ulong t0)
+void helper_mtc0_tcrestart (target_ulong arg1)
 {
-    env->active_tc.PC = t0;
+    env->active_tc.PC = arg1;
     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
     env->CP0_LLAddr = 0ULL;
     /* MIPS16 not implemented. */
 }
 
-void do_mttc0_tcrestart (target_ulong t0)
+void helper_mttc0_tcrestart (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc) {
-        env->active_tc.PC = t0;
+        env->active_tc.PC = arg1;
         env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
         env->CP0_LLAddr = 0ULL;
         /* MIPS16 not implemented. */
     } else {
-        env->tcs[other_tc].PC = t0;
+        env->tcs[other_tc].PC = arg1;
         env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
         env->CP0_LLAddr = 0ULL;
         /* MIPS16 not implemented. */
     }
 }
 
-void do_mtc0_tchalt (target_ulong t0)
+void helper_mtc0_tchalt (target_ulong arg1)
 {
-    env->active_tc.CP0_TCHalt = t0 & 0x1;
+    env->active_tc.CP0_TCHalt = arg1 & 0x1;
 
     // TODO: Halt TC / Restart (if allocated+active) TC.
 }
 
-void do_mttc0_tchalt (target_ulong t0)
+void helper_mttc0_tchalt (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     // TODO: Halt TC / Restart (if allocated+active) TC.
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCHalt = t0;
+        env->active_tc.CP0_TCHalt = arg1;
     else
-        env->tcs[other_tc].CP0_TCHalt = t0;
+        env->tcs[other_tc].CP0_TCHalt = arg1;
 }
 
-void do_mtc0_tccontext (target_ulong t0)
+void helper_mtc0_tccontext (target_ulong arg1)
 {
-    env->active_tc.CP0_TCContext = t0;
+    env->active_tc.CP0_TCContext = arg1;
 }
 
-void do_mttc0_tccontext (target_ulong t0)
+void helper_mttc0_tccontext (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCContext = t0;
+        env->active_tc.CP0_TCContext = arg1;
     else
-        env->tcs[other_tc].CP0_TCContext = t0;
+        env->tcs[other_tc].CP0_TCContext = arg1;
 }
 
-void do_mtc0_tcschedule (target_ulong t0)
+void helper_mtc0_tcschedule (target_ulong arg1)
 {
-    env->active_tc.CP0_TCSchedule = t0;
+    env->active_tc.CP0_TCSchedule = arg1;
 }
 
-void do_mttc0_tcschedule (target_ulong t0)
+void helper_mttc0_tcschedule (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCSchedule = t0;
+        env->active_tc.CP0_TCSchedule = arg1;
     else
-        env->tcs[other_tc].CP0_TCSchedule = t0;
+        env->tcs[other_tc].CP0_TCSchedule = arg1;
 }
 
-void do_mtc0_tcschefback (target_ulong t0)
+void helper_mtc0_tcschefback (target_ulong arg1)
 {
-    env->active_tc.CP0_TCScheFBack = t0;
+    env->active_tc.CP0_TCScheFBack = arg1;
 }
 
-void do_mttc0_tcschefback (target_ulong t0)
+void helper_mttc0_tcschefback (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCScheFBack = t0;
+        env->active_tc.CP0_TCScheFBack = arg1;
     else
-        env->tcs[other_tc].CP0_TCScheFBack = t0;
+        env->tcs[other_tc].CP0_TCScheFBack = arg1;
 }
 
-void do_mtc0_entrylo1 (target_ulong t0)
+void helper_mtc0_entrylo1 (target_ulong arg1)
 {
     /* Large physaddr (PABITS) not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
+    env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
 }
 
-void do_mtc0_context (target_ulong t0)
+void helper_mtc0_context (target_ulong arg1)
 {
-    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
+    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
 }
 
-void do_mtc0_pagemask (target_ulong t0)
+void helper_mtc0_pagemask (target_ulong arg1)
 {
     /* 1k pages not implemented */
-    env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
+    env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
 }
 
-void do_mtc0_pagegrain (target_ulong t0)
+void helper_mtc0_pagegrain (target_ulong arg1)
 {
     /* SmartMIPS not implemented */
     /* Large physaddr (PABITS) not implemented */
@@ -1102,52 +1070,52 @@ void do_mtc0_pagegrain (target_ulong t0)
     env->CP0_PageGrain = 0;
 }
 
-void do_mtc0_wired (target_ulong t0)
+void helper_mtc0_wired (target_ulong arg1)
 {
-    env->CP0_Wired = t0 % env->tlb->nb_tlb;
+    env->CP0_Wired = arg1 % env->tlb->nb_tlb;
 }
 
-void do_mtc0_srsconf0 (target_ulong t0)
+void helper_mtc0_srsconf0 (target_ulong arg1)
 {
-    env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
+    env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
 }
 
-void do_mtc0_srsconf1 (target_ulong t0)
+void helper_mtc0_srsconf1 (target_ulong arg1)
 {
-    env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
+    env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
 }
 
-void do_mtc0_srsconf2 (target_ulong t0)
+void helper_mtc0_srsconf2 (target_ulong arg1)
 {
-    env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
+    env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
 }
 
-void do_mtc0_srsconf3 (target_ulong t0)
+void helper_mtc0_srsconf3 (target_ulong arg1)
 {
-    env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
+    env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
 }
 
-void do_mtc0_srsconf4 (target_ulong t0)
+void helper_mtc0_srsconf4 (target_ulong arg1)
 {
-    env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
+    env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
 }
 
-void do_mtc0_hwrena (target_ulong t0)
+void helper_mtc0_hwrena (target_ulong arg1)
 {
-    env->CP0_HWREna = t0 & 0x0000000F;
+    env->CP0_HWREna = arg1 & 0x0000000F;
 }
 
-void do_mtc0_count (target_ulong t0)
+void helper_mtc0_count (target_ulong arg1)
 {
-    cpu_mips_store_count(env, t0);
+    cpu_mips_store_count(env, arg1);
 }
 
-void do_mtc0_entryhi (target_ulong t0)
+void helper_mtc0_entryhi (target_ulong arg1)
 {
     target_ulong old, val;
 
     /* 1k pages not implemented */
-    val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
+    val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
 #if defined(TARGET_MIPS64)
     val &= env->SEGMask;
 #endif
@@ -1162,68 +1130,78 @@ void do_mtc0_entryhi (target_ulong t0)
         cpu_mips_tlb_flush(env, 1);
 }
 
-void do_mttc0_entryhi(target_ulong t0)
+void helper_mttc0_entryhi(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     int32_t tcstatus;
 
-    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
+    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
     if (other_tc == env->current_tc) {
-        tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff);
+        tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
         env->active_tc.CP0_TCStatus = tcstatus;
     } else {
-        tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff);
+        tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
         env->tcs[other_tc].CP0_TCStatus = tcstatus;
     }
 }
 
-void do_mtc0_compare (target_ulong t0)
+void helper_mtc0_compare (target_ulong arg1)
 {
-    cpu_mips_store_compare(env, t0);
+    cpu_mips_store_compare(env, arg1);
 }
 
-void do_mtc0_status (target_ulong t0)
+void helper_mtc0_status (target_ulong arg1)
 {
     uint32_t val, old;
     uint32_t mask = env->CP0_Status_rw_bitmask;
 
-    val = t0 & mask;
+    val = arg1 & mask;
     old = env->CP0_Status;
     env->CP0_Status = (env->CP0_Status & ~mask) | val;
     compute_hflags(env);
-    if (loglevel & CPU_LOG_EXEC)
-        do_mtc0_status_debug(old, val);
+    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
+        qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
+                old, old & env->CP0_Cause & CP0Ca_IP_mask,
+                val, val & env->CP0_Cause & CP0Ca_IP_mask,
+                env->CP0_Cause);
+        switch (env->hflags & MIPS_HFLAG_KSU) {
+        case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
+        case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
+        case MIPS_HFLAG_KM: qemu_log("\n"); break;
+        default: cpu_abort(env, "Invalid MMU mode!\n"); break;
+       }
+    }
     cpu_mips_update_irq(env);
 }
 
-void do_mttc0_status(target_ulong t0)
+void helper_mttc0_status(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
 
-    env->CP0_Status = t0 & ~0xf1000018;
-    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
-    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
-    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
+    env->CP0_Status = arg1 & ~0xf1000018;
+    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
+    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
+    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
     if (other_tc == env->current_tc)
         env->active_tc.CP0_TCStatus = tcstatus;
     else
         env->tcs[other_tc].CP0_TCStatus = tcstatus;
 }
 
-void do_mtc0_intctl (target_ulong t0)
+void helper_mtc0_intctl (target_ulong arg1)
 {
     /* vectored interrupts not implemented, no performance counters. */
-    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
+    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
 }
 
-void do_mtc0_srsctl (target_ulong t0)
+void helper_mtc0_srsctl (target_ulong arg1)
 {
     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
-    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
+    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
 }
 
-void do_mtc0_cause (target_ulong t0)
+void helper_mtc0_cause (target_ulong arg1)
 {
     uint32_t mask = 0x00C00300;
     uint32_t old = env->CP0_Cause;
@@ -1231,7 +1209,7 @@ void do_mtc0_cause (target_ulong t0)
     if (env->insn_flags & ISA_MIPS32R2)
         mask |= 1 << CP0Ca_DC;
 
-    env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
+    env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
 
     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
         if (env->CP0_Cause & (1 << CP0Ca_DC))
@@ -1242,66 +1220,66 @@ void do_mtc0_cause (target_ulong t0)
 
     /* Handle the software interrupt as an hardware one, as they
        are very similar */
-    if (t0 & CP0Ca_IP_mask) {
+    if (arg1 & CP0Ca_IP_mask) {
         cpu_mips_update_irq(env);
     }
 }
 
-void do_mtc0_ebase (target_ulong t0)
+void helper_mtc0_ebase (target_ulong arg1)
 {
     /* vectored interrupts not implemented */
     /* Multi-CPU not implemented */
-    env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
+    env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
 }
 
-void do_mtc0_config0 (target_ulong t0)
+void helper_mtc0_config0 (target_ulong arg1)
 {
-    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
+    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
 }
 
-void do_mtc0_config2 (target_ulong t0)
+void helper_mtc0_config2 (target_ulong arg1)
 {
     /* tertiary/secondary caches not implemented */
     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
 }
 
-void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
+void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
 {
     /* Watch exceptions for instructions, data loads, data stores
        not implemented. */
-    env->CP0_WatchLo[sel] = (t0 & ~0x7);
+    env->CP0_WatchLo[sel] = (arg1 & ~0x7);
 }
 
-void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
+void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
 {
-    env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
-    env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
+    env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
+    env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
 }
 
-void do_mtc0_xcontext (target_ulong t0)
+void helper_mtc0_xcontext (target_ulong arg1)
 {
     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
-    env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
+    env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
 }
 
-void do_mtc0_framemask (target_ulong t0)
+void helper_mtc0_framemask (target_ulong arg1)
 {
-    env->CP0_Framemask = t0; /* XXX */
+    env->CP0_Framemask = arg1; /* XXX */
 }
 
-void do_mtc0_debug (target_ulong t0)
+void helper_mtc0_debug (target_ulong arg1)
 {
-    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
-    if (t0 & (1 << CP0DB_DM))
+    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
+    if (arg1 & (1 << CP0DB_DM))
         env->hflags |= MIPS_HFLAG_DM;
     else
         env->hflags &= ~MIPS_HFLAG_DM;
 }
 
-void do_mttc0_debug(target_ulong t0)
+void helper_mttc0_debug(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
-    uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
+    uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
 
     /* XXX: Might be wrong, check with EJTAG spec. */
     if (other_tc == env->current_tc)
@@ -1309,56 +1287,36 @@ void do_mttc0_debug(target_ulong t0)
     else
         env->tcs[other_tc].CP0_Debug_tcstatus = val;
     env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
-                     (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
-}
-
-void do_mtc0_performance0 (target_ulong t0)
-{
-    env->CP0_Performance0 = t0 & 0x000007ff;
-}
-
-void do_mtc0_taglo (target_ulong t0)
-{
-    env->CP0_TagLo = t0 & 0xFFFFFCF6;
+                     (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 }
 
-void do_mtc0_datalo (target_ulong t0)
+void helper_mtc0_performance0 (target_ulong arg1)
 {
-    env->CP0_DataLo = t0; /* XXX */
+    env->CP0_Performance0 = arg1 & 0x000007ff;
 }
 
-void do_mtc0_taghi (target_ulong t0)
+void helper_mtc0_taglo (target_ulong arg1)
 {
-    env->CP0_TagHi = t0; /* XXX */
+    env->CP0_TagLo = arg1 & 0xFFFFFCF6;
 }
 
-void do_mtc0_datahi (target_ulong t0)
+void helper_mtc0_datalo (target_ulong arg1)
 {
-    env->CP0_DataHi = t0; /* XXX */
+    env->CP0_DataLo = arg1; /* XXX */
 }
 
-void do_mtc0_status_debug(uint32_t old, uint32_t val)
+void helper_mtc0_taghi (target_ulong arg1)
 {
-    fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
-            old, old & env->CP0_Cause & CP0Ca_IP_mask,
-            val, val & env->CP0_Cause & CP0Ca_IP_mask,
-            env->CP0_Cause);
-    switch (env->hflags & MIPS_HFLAG_KSU) {
-    case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
-    case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
-    case MIPS_HFLAG_KM: fputs("\n", logfile); break;
-    default: cpu_abort(env, "Invalid MMU mode!\n"); break;
-    }
+    env->CP0_TagHi = arg1; /* XXX */
 }
 
-void do_mtc0_status_irqraise_debug(void)
+void helper_mtc0_datahi (target_ulong arg1)
 {
-    fprintf(logfile, "Raise pending IRQs\n");
+    env->CP0_DataHi = arg1; /* XXX */
 }
-#endif /* !CONFIG_USER_ONLY */
 
 /* MIPS MT functions */
-target_ulong do_mftgpr(target_ulong t0, uint32_t sel)
+target_ulong helper_mftgpr(uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -1368,7 +1326,7 @@ target_ulong do_mftgpr(target_ulong t0, uint32_t sel)
         return env->tcs[other_tc].gpr[sel];
 }
 
-target_ulong do_mftlo(target_ulong t0, uint32_t sel)
+target_ulong helper_mftlo(uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -1378,7 +1336,7 @@ target_ulong do_mftlo(target_ulong t0, uint32_t sel)
         return env->tcs[other_tc].LO[sel];
 }
 
-target_ulong do_mfthi(target_ulong t0, uint32_t sel)
+target_ulong helper_mfthi(uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -1388,7 +1346,7 @@ target_ulong do_mfthi(target_ulong t0, uint32_t sel)
         return env->tcs[other_tc].HI[sel];
 }
 
-target_ulong do_mftacx(target_ulong t0, uint32_t sel)
+target_ulong helper_mftacx(uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -1398,7 +1356,7 @@ target_ulong do_mftacx(target_ulong t0, uint32_t sel)
         return env->tcs[other_tc].ACX[sel];
 }
 
-target_ulong do_mftdsp(target_ulong t0)
+target_ulong helper_mftdsp(void)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
@@ -1408,124 +1366,125 @@ target_ulong do_mftdsp(target_ulong t0)
         return env->tcs[other_tc].DSPControl;
 }
 
-void do_mttgpr(target_ulong t0, uint32_t sel)
+void helper_mttgpr(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.gpr[sel] = t0;
+        env->active_tc.gpr[sel] = arg1;
     else
-        env->tcs[other_tc].gpr[sel] = t0;
+        env->tcs[other_tc].gpr[sel] = arg1;
 }
 
-void do_mttlo(target_ulong t0, uint32_t sel)
+void helper_mttlo(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.LO[sel] = t0;
+        env->active_tc.LO[sel] = arg1;
     else
-        env->tcs[other_tc].LO[sel] = t0;
+        env->tcs[other_tc].LO[sel] = arg1;
 }
 
-void do_mtthi(target_ulong t0, uint32_t sel)
+void helper_mtthi(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.HI[sel] = t0;
+        env->active_tc.HI[sel] = arg1;
     else
-        env->tcs[other_tc].HI[sel] = t0;
+        env->tcs[other_tc].HI[sel] = arg1;
 }
 
-void do_mttacx(target_ulong t0, uint32_t sel)
+void helper_mttacx(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.ACX[sel] = t0;
+        env->active_tc.ACX[sel] = arg1;
     else
-        env->tcs[other_tc].ACX[sel] = t0;
+        env->tcs[other_tc].ACX[sel] = arg1;
 }
 
-void do_mttdsp(target_ulong t0)
+void helper_mttdsp(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.DSPControl = t0;
+        env->active_tc.DSPControl = arg1;
     else
-        env->tcs[other_tc].DSPControl = t0;
+        env->tcs[other_tc].DSPControl = arg1;
 }
 
 /* MIPS MT functions */
-target_ulong do_dmt(target_ulong t0)
+target_ulong helper_dmt(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_emt(target_ulong t0)
+target_ulong helper_emt(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_dvpe(target_ulong t0)
+target_ulong helper_dvpe(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
 
-target_ulong do_evpe(target_ulong t0)
+target_ulong helper_evpe(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
+#endif /* !CONFIG_USER_ONLY */
 
-void do_fork(target_ulong t0, target_ulong t1)
+void helper_fork(target_ulong arg1, target_ulong arg2)
 {
-    // t0 = rt, t1 = rs
-    t0 = 0;
+    // arg1 = rt, arg2 = rs
+    arg1 = 0;
     // TODO: store to TC register
 }
 
-target_ulong do_yield(target_ulong t0)
+target_ulong helper_yield(target_ulong arg1)
 {
-    if (t0 < 0) {
+    if (arg1 < 0) {
         /* No scheduling policy implemented. */
-        if (t0 != -2) {
+        if (arg1 != -2) {
             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
-                do_raise_exception(EXCP_THREAD);
+                helper_raise_exception(EXCP_THREAD);
             }
         }
-    } else if (t0 == 0) {
-       if (0 /* TODO: TC underflow */) {
+    } else if (arg1 == 0) {
+        if (0 /* TODO: TC underflow */) {
             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
-            do_raise_exception(EXCP_THREAD);
+            helper_raise_exception(EXCP_THREAD);
         } else {
             // TODO: Deallocate TC
         }
-    } else if (t0 > 0) {
+    } else if (arg1 > 0) {
         /* Yield qualifier inputs not implemented. */
         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
-        do_raise_exception(EXCP_THREAD);
+        helper_raise_exception(EXCP_THREAD);
     }
     return env->CP0_YQMask;
 }
@@ -1570,7 +1529,7 @@ static void r4k_fill_tlb (int idx)
     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
 }
 
-void r4k_do_tlbwi (void)
+void r4k_helper_tlbwi (void)
 {
     int idx;
 
@@ -1585,7 +1544,7 @@ void r4k_do_tlbwi (void)
     r4k_fill_tlb(idx);
 }
 
-void r4k_do_tlbwr (void)
+void r4k_helper_tlbwr (void)
 {
     int r = cpu_mips_get_random(env);
 
@@ -1593,7 +1552,7 @@ void r4k_do_tlbwr (void)
     r4k_fill_tlb(r);
 }
 
-void r4k_do_tlbp (void)
+void r4k_helper_tlbp (void)
 {
     r4k_tlb_t *tlb;
     target_ulong mask;
@@ -1619,23 +1578,23 @@ void r4k_do_tlbp (void)
     if (i == env->tlb->nb_tlb) {
         /* No match.  Discard any shadow entries, if any of them match.  */
         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
-           tlb = &env->tlb->mmu.r4k.tlb[i];
-           /* 1k pages are not supported. */
-           mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
-           tag = env->CP0_EntryHi & ~mask;
-           VPN = tlb->VPN & ~mask;
-           /* Check ASID, virtual page number & size */
-           if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
+            tlb = &env->tlb->mmu.r4k.tlb[i];
+            /* 1k pages are not supported. */
+            mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
+            tag = env->CP0_EntryHi & ~mask;
+            VPN = tlb->VPN & ~mask;
+            /* Check ASID, virtual page number & size */
+            if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
                 r4k_mips_tlb_flush_extra (env, i);
-               break;
-           }
-       }
+                break;
+            }
+        }
 
         env->CP0_Index |= 0x80000000;
     }
 }
 
-void r4k_do_tlbr (void)
+void r4k_helper_tlbr (void)
 {
     r4k_tlb_t *tlb;
     uint8_t ASID;
@@ -1659,8 +1618,28 @@ void r4k_do_tlbr (void)
                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
 }
 
+void helper_tlbwi(void)
+{
+    env->tlb->helper_tlbwi();
+}
+
+void helper_tlbwr(void)
+{
+    env->tlb->helper_tlbwr();
+}
+
+void helper_tlbp(void)
+{
+    env->tlb->helper_tlbp();
+}
+
+void helper_tlbr(void)
+{
+    env->tlb->helper_tlbr();
+}
+
 /* Specials */
-target_ulong do_di (void)
+target_ulong helper_di (void)
 {
     target_ulong t0 = env->CP0_Status;
 
@@ -1670,7 +1649,7 @@ target_ulong do_di (void)
     return t0;
 }
 
-target_ulong do_ei (void)
+target_ulong helper_ei (void)
 {
     target_ulong t0 = env->CP0_Status;
 
@@ -1680,37 +1659,40 @@ target_ulong do_ei (void)
     return t0;
 }
 
-void debug_pre_eret (void)
+static void debug_pre_eret (void)
 {
-    fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
-            env->active_tc.PC, env->CP0_EPC);
-    if (env->CP0_Status & (1 << CP0St_ERL))
-        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
-    if (env->hflags & MIPS_HFLAG_DM)
-        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
-    fputs("\n", logfile);
+    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
+        qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
+                env->active_tc.PC, env->CP0_EPC);
+        if (env->CP0_Status & (1 << CP0St_ERL))
+            qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
+        if (env->hflags & MIPS_HFLAG_DM)
+            qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
+        qemu_log("\n");
+    }
 }
 
-void debug_post_eret (void)
-{
-    fprintf(logfile, "  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
-            env->active_tc.PC, env->CP0_EPC);
-    if (env->CP0_Status & (1 << CP0St_ERL))
-        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
-    if (env->hflags & MIPS_HFLAG_DM)
-        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
-    switch (env->hflags & MIPS_HFLAG_KSU) {
-    case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
-    case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
-    case MIPS_HFLAG_KM: fputs("\n", logfile); break;
-    default: cpu_abort(env, "Invalid MMU mode!\n"); break;
+static void debug_post_eret (void)
+{
+    if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
+        qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
+                env->active_tc.PC, env->CP0_EPC);
+        if (env->CP0_Status & (1 << CP0St_ERL))
+            qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
+        if (env->hflags & MIPS_HFLAG_DM)
+            qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
+        switch (env->hflags & MIPS_HFLAG_KSU) {
+        case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
+        case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
+        case MIPS_HFLAG_KM: qemu_log("\n"); break;
+        default: cpu_abort(env, "Invalid MMU mode!\n"); break;
+        }
     }
 }
 
-void do_eret (void)
+void helper_eret (void)
 {
-    if (loglevel & CPU_LOG_EXEC)
-        debug_pre_eret();
+    debug_pre_eret();
     if (env->CP0_Status & (1 << CP0St_ERL)) {
         env->active_tc.PC = env->CP0_ErrorEPC;
         env->CP0_Status &= ~(1 << CP0St_ERL);
@@ -1719,112 +1701,66 @@ void do_eret (void)
         env->CP0_Status &= ~(1 << CP0St_EXL);
     }
     compute_hflags(env);
-    if (loglevel & CPU_LOG_EXEC)
-        debug_post_eret();
+    debug_post_eret();
     env->CP0_LLAddr = 1;
 }
 
-void do_deret (void)
+void helper_deret (void)
 {
-    if (loglevel & CPU_LOG_EXEC)
-        debug_pre_eret();
+    debug_pre_eret();
     env->active_tc.PC = env->CP0_DEPC;
     env->hflags &= MIPS_HFLAG_DM;
     compute_hflags(env);
-    if (loglevel & CPU_LOG_EXEC)
-        debug_post_eret();
+    debug_post_eret();
     env->CP0_LLAddr = 1;
 }
 #endif /* !CONFIG_USER_ONLY */
 
-target_ulong do_rdhwr_cpunum(void)
+target_ulong helper_rdhwr_cpunum(void)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 0)))
         return env->CP0_EBase & 0x3ff;
     else
-        do_raise_exception(EXCP_RI);
+        helper_raise_exception(EXCP_RI);
 
     return 0;
 }
 
-target_ulong do_rdhwr_synci_step(void)
+target_ulong helper_rdhwr_synci_step(void)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 1)))
         return env->SYNCI_Step;
     else
-        do_raise_exception(EXCP_RI);
+        helper_raise_exception(EXCP_RI);
 
     return 0;
 }
 
-target_ulong do_rdhwr_cc(void)
+target_ulong helper_rdhwr_cc(void)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 2)))
         return env->CP0_Count;
     else
-        do_raise_exception(EXCP_RI);
+        helper_raise_exception(EXCP_RI);
 
     return 0;
 }
 
-target_ulong do_rdhwr_ccres(void)
+target_ulong helper_rdhwr_ccres(void)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 3)))
         return env->CCRes;
     else
-        do_raise_exception(EXCP_RI);
+        helper_raise_exception(EXCP_RI);
 
     return 0;
 }
 
-/* Bitfield operations. */
-target_ulong do_ext(target_ulong t1, uint32_t pos, uint32_t size)
-{
-    return (int32_t)((t1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
-}
-
-target_ulong do_ins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
-{
-    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
-
-    return (int32_t)((t0 & ~mask) | ((t1 << pos) & mask));
-}
-
-target_ulong do_wsbh(target_ulong t1)
-{
-    return (int32_t)(((t1 << 8) & ~0x00FF00FF) | ((t1 >> 8) & 0x00FF00FF));
-}
-
-#if defined(TARGET_MIPS64)
-target_ulong do_dext(target_ulong t1, uint32_t pos, uint32_t size)
-{
-    return (t1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
-}
-
-target_ulong do_dins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
-{
-    target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
-
-    return (t0 & ~mask) | ((t1 << pos) & mask);
-}
-
-target_ulong do_dsbh(target_ulong t1)
-{
-    return ((t1 << 8) & ~0x00FF00FF00FF00FFULL) | ((t1 >> 8) & 0x00FF00FF00FF00FFULL);
-}
-
-target_ulong do_dshd(target_ulong t1)
-{
-    t1 = ((t1 << 16) & ~0x0000FFFF0000FFFFULL) | ((t1 >> 16) & 0x0000FFFF0000FFFFULL);
-    return (t1 << 32) | (t1 >> 32);
-}
-#endif
-
-void do_pmon (int function)
+void helper_pmon (int function)
 {
     function /= 2;
     switch (function) {
@@ -1850,10 +1786,10 @@ void do_pmon (int function)
     }
 }
 
-void do_wait (void)
+void helper_wait (void)
 {
     env->halted = 1;
-    do_raise_exception(EXCP_HLT);
+    helper_raise_exception(EXCP_HLT);
 }
 
 #if !defined(CONFIG_USER_ONLY)
@@ -1879,7 +1815,7 @@ static void do_unaligned_access (target_ulong addr, int is_write, int is_user, v
 {
     env->CP0_BadVAddr = addr;
     do_restore_state (retaddr);
-    do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
+    helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
 }
 
 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
@@ -1905,18 +1841,18 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
                 cpu_restore_state(tb, env, pc, NULL);
             }
         }
-        do_raise_exception_err(env->exception_index, env->error_code);
+        helper_raise_exception_err(env->exception_index, env->error_code);
     }
     env = saved_env;
 }
 
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
-                          int unused)
+                          int unused, int size)
 {
     if (is_exec)
-        do_raise_exception(EXCP_IBE);
+        helper_raise_exception(EXCP_IBE);
     else
-        do_raise_exception(EXCP_DBE);
+        helper_raise_exception(EXCP_DBE);
 }
 #endif /* !CONFIG_USER_ONLY */
 
@@ -1932,7 +1868,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 #define FLOAT_SNAN64 0x7fffffffffffffffULL
 
 /* convert MIPS rounding mode in FCR31 to IEEE library */
-unsigned int ieee_rm[] = {
+static unsigned int ieee_rm[] = {
     float_round_nearest_even,
     float_round_to_zero,
     float_round_up,
@@ -1940,66 +1876,71 @@ unsigned int ieee_rm[] = {
 };
 
 #define RESTORE_ROUNDING_MODE \
-    set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
+    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
 
-target_ulong do_cfc1 (uint32_t reg)
+#define RESTORE_FLUSH_MODE \
+    set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
+
+target_ulong helper_cfc1 (uint32_t reg)
 {
-    target_ulong t0;
+    target_ulong arg1;
 
     switch (reg) {
     case 0:
-        t0 = (int32_t)env->fpu->fcr0;
+        arg1 = (int32_t)env->active_fpu.fcr0;
         break;
     case 25:
-        t0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
+        arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
         break;
     case 26:
-        t0 = env->fpu->fcr31 & 0x0003f07c;
+        arg1 = env->active_fpu.fcr31 & 0x0003f07c;
         break;
     case 28:
-        t0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
+        arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
         break;
     default:
-        t0 = (int32_t)env->fpu->fcr31;
+        arg1 = (int32_t)env->active_fpu.fcr31;
         break;
     }
 
-    return t0;
+    return arg1;
 }
 
-void do_ctc1 (target_ulong t0, uint32_t reg)
+void helper_ctc1 (target_ulong arg1, uint32_t reg)
 {
     switch(reg) {
     case 25:
-        if (t0 & 0xffffff00)
+        if (arg1 & 0xffffff00)
             return;
-        env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
-                     ((t0 & 0x1) << 23);
+        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
+                     ((arg1 & 0x1) << 23);
         break;
     case 26:
-        if (t0 & 0x007c0000)
+        if (arg1 & 0x007c0000)
             return;
-        env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
+        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
         break;
     case 28:
-        if (t0 & 0x007c0000)
+        if (arg1 & 0x007c0000)
             return;
-        env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
-                     ((t0 & 0x4) << 22);
+        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
+                     ((arg1 & 0x4) << 22);
         break;
     case 31:
-        if (t0 & 0x007c0000)
+        if (arg1 & 0x007c0000)
             return;
-        env->fpu->fcr31 = t0;
+        env->active_fpu.fcr31 = arg1;
         break;
     default:
         return;
     }
     /* set rounding mode */
     RESTORE_ROUNDING_MODE;
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
-        do_raise_exception(EXCP_FPE);
+    /* set flush-to-zero mode */
+    RESTORE_FLUSH_MODE;
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
+        helper_raise_exception(EXCP_FPE);
 }
 
 static inline char ieee_ex_to_mips(char xcpt)
@@ -2022,13 +1963,13 @@ static inline char mips_ex_to_ieee(char xcpt)
 
 static inline void update_fcr31(void)
 {
-    int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
+    int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
 
-    SET_FP_CAUSE(env->fpu->fcr31, tmp);
-    if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
-        do_raise_exception(EXCP_FPE);
+    SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
+    if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
+        helper_raise_exception(EXCP_FPE);
     else
-        UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
+        UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
 }
 
 /* Float support.
@@ -2037,383 +1978,383 @@ static inline void update_fcr31(void)
    paired single lower "pl", paired single upper "pu".  */
 
 /* unary operations, modifying fp status  */
-uint64_t do_float_sqrt_d(uint64_t fdt0)
+uint64_t helper_float_sqrt_d(uint64_t fdt0)
 {
-    return float64_sqrt(fdt0, &env->fpu->fp_status);
+    return float64_sqrt(fdt0, &env->active_fpu.fp_status);
 }
 
-uint32_t do_float_sqrt_s(uint32_t fst0)
+uint32_t helper_float_sqrt_s(uint32_t fst0)
 {
-    return float32_sqrt(fst0, &env->fpu->fp_status);
+    return float32_sqrt(fst0, &env->active_fpu.fp_status);
 }
 
-uint64_t do_float_cvtd_s(uint32_t fst0)
+uint64_t helper_float_cvtd_s(uint32_t fst0)
 {
     uint64_t fdt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = float32_to_float64(fst0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
     update_fcr31();
     return fdt2;
 }
 
-uint64_t do_float_cvtd_w(uint32_t wt0)
+uint64_t helper_float_cvtd_w(uint32_t wt0)
 {
     uint64_t fdt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = int32_to_float64(wt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
     update_fcr31();
     return fdt2;
 }
 
-uint64_t do_float_cvtd_l(uint64_t dt0)
+uint64_t helper_float_cvtd_l(uint64_t dt0)
 {
     uint64_t fdt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = int64_to_float64(dt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
     update_fcr31();
     return fdt2;
 }
 
-uint64_t do_float_cvtl_d(uint64_t fdt0)
+uint64_t helper_float_cvtl_d(uint64_t fdt0)
 {
     uint64_t dt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint64_t do_float_cvtl_s(uint32_t fst0)
+uint64_t helper_float_cvtl_s(uint32_t fst0)
 {
     uint64_t dt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint64_t do_float_cvtps_pw(uint64_t dt0)
+uint64_t helper_float_cvtps_pw(uint64_t dt0)
 {
     uint32_t fst2;
     uint32_t fsth2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->fpu->fp_status);
-    fsth2 = int32_to_float32(dt0 >> 32, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+    fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
     update_fcr31();
     return ((uint64_t)fsth2 << 32) | fst2;
 }
 
-uint64_t do_float_cvtpw_ps(uint64_t fdt0)
+uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
 {
     uint32_t wt2;
     uint32_t wth2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);
-    wth2 = float32_to_int32(fdt0 >> 32, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+    wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID)) {
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
         wt2 = FLOAT_SNAN32;
         wth2 = FLOAT_SNAN32;
     }
     return ((uint64_t)wth2 << 32) | wt2;
 }
 
-uint32_t do_float_cvts_d(uint64_t fdt0)
+uint32_t helper_float_cvts_d(uint64_t fdt0)
 {
     uint32_t fst2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float64_to_float32(fdt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
     update_fcr31();
     return fst2;
 }
 
-uint32_t do_float_cvts_w(uint32_t wt0)
+uint32_t helper_float_cvts_w(uint32_t wt0)
 {
     uint32_t fst2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = int32_to_float32(wt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
     update_fcr31();
     return fst2;
 }
 
-uint32_t do_float_cvts_l(uint64_t dt0)
+uint32_t helper_float_cvts_l(uint64_t dt0)
 {
     uint32_t fst2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = int64_to_float32(dt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
     update_fcr31();
     return fst2;
 }
 
-uint32_t do_float_cvts_pl(uint32_t wt0)
+uint32_t helper_float_cvts_pl(uint32_t wt0)
 {
     uint32_t wt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
     wt2 = wt0;
     update_fcr31();
     return wt2;
 }
 
-uint32_t do_float_cvts_pu(uint32_t wth0)
+uint32_t helper_float_cvts_pu(uint32_t wth0)
 {
     uint32_t wt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
     wt2 = wth0;
     update_fcr31();
     return wt2;
 }
 
-uint32_t do_float_cvtw_s(uint32_t fst0)
+uint32_t helper_float_cvtw_s(uint32_t fst0)
 {
     uint32_t wt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint32_t do_float_cvtw_d(uint64_t fdt0)
+uint32_t helper_float_cvtw_d(uint64_t fdt0)
 {
     uint32_t wt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint64_t do_float_roundl_d(uint64_t fdt0)
+uint64_t helper_float_roundl_d(uint64_t fdt0)
 {
     uint64_t dt2;
 
-    set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
-    dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+    dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint64_t do_float_roundl_s(uint32_t fst0)
+uint64_t helper_float_roundl_s(uint32_t fst0)
 {
     uint64_t dt2;
 
-    set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
-    dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+    dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint32_t do_float_roundw_d(uint64_t fdt0)
+uint32_t helper_float_roundw_d(uint64_t fdt0)
 {
     uint32_t wt2;
 
-    set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
-    wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+    wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint32_t do_float_roundw_s(uint32_t fst0)
+uint32_t helper_float_roundw_s(uint32_t fst0)
 {
     uint32_t wt2;
 
-    set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
-    wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+    wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint64_t do_float_truncl_d(uint64_t fdt0)
+uint64_t helper_float_truncl_d(uint64_t fdt0)
 {
     uint64_t dt2;
 
-    dt2 = float64_to_int64_round_to_zero(fdt0, &env->fpu->fp_status);
+    dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint64_t do_float_truncl_s(uint32_t fst0)
+uint64_t helper_float_truncl_s(uint32_t fst0)
 {
     uint64_t dt2;
 
-    dt2 = float32_to_int64_round_to_zero(fst0, &env->fpu->fp_status);
+    dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint32_t do_float_truncw_d(uint64_t fdt0)
+uint32_t helper_float_truncw_d(uint64_t fdt0)
 {
     uint32_t wt2;
 
-    wt2 = float64_to_int32_round_to_zero(fdt0, &env->fpu->fp_status);
+    wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint32_t do_float_truncw_s(uint32_t fst0)
+uint32_t helper_float_truncw_s(uint32_t fst0)
 {
     uint32_t wt2;
 
-    wt2 = float32_to_int32_round_to_zero(fst0, &env->fpu->fp_status);
+    wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint64_t do_float_ceill_d(uint64_t fdt0)
+uint64_t helper_float_ceill_d(uint64_t fdt0)
 {
     uint64_t dt2;
 
-    set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
-    dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+    dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint64_t do_float_ceill_s(uint32_t fst0)
+uint64_t helper_float_ceill_s(uint32_t fst0)
 {
     uint64_t dt2;
 
-    set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
-    dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+    dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint32_t do_float_ceilw_d(uint64_t fdt0)
+uint32_t helper_float_ceilw_d(uint64_t fdt0)
 {
     uint32_t wt2;
 
-    set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
-    wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+    wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint32_t do_float_ceilw_s(uint32_t fst0)
+uint32_t helper_float_ceilw_s(uint32_t fst0)
 {
     uint32_t wt2;
 
-    set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
-    wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
+    wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint64_t do_float_floorl_d(uint64_t fdt0)
+uint64_t helper_float_floorl_d(uint64_t fdt0)
 {
     uint64_t dt2;
 
-    set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
-    dt2 = float64_to_int64(fdt0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+    dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint64_t do_float_floorl_s(uint32_t fst0)
+uint64_t helper_float_floorl_s(uint32_t fst0)
 {
     uint64_t dt2;
 
-    set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
-    dt2 = float32_to_int64(fst0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+    dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         dt2 = FLOAT_SNAN64;
     return dt2;
 }
 
-uint32_t do_float_floorw_d(uint64_t fdt0)
+uint32_t helper_float_floorw_d(uint64_t fdt0)
 {
     uint32_t wt2;
 
-    set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
-    wt2 = float64_to_int32(fdt0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+    wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
-uint32_t do_float_floorw_s(uint32_t fst0)
+uint32_t helper_float_floorw_s(uint32_t fst0)
 {
     uint32_t wt2;
 
-    set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
-    wt2 = float32_to_int32(fst0, &env->fpu->fp_status);
+    set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
+    wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
     RESTORE_ROUNDING_MODE;
     update_fcr31();
-    if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
         wt2 = FLOAT_SNAN32;
     return wt2;
 }
 
 /* unary operations, not modifying fp status  */
 #define FLOAT_UNOP(name)                                       \
-uint64_t do_float_ ## name ## _d(uint64_t fdt0)                \
+uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
 {                                                              \
     return float64_ ## name(fdt0);                             \
 }                                                              \
-uint32_t do_float_ ## name ## _s(uint32_t fst0)                \
+uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
 {                                                              \
     return float32_ ## name(fst0);                             \
 }                                                              \
-uint64_t do_float_ ## name ## _ps(uint64_t fdt0)               \
+uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
 {                                                              \
     uint32_t wt0;                                              \
     uint32_t wth0;                                             \
@@ -2427,145 +2368,145 @@ FLOAT_UNOP(chs)
 #undef FLOAT_UNOP
 
 /* MIPS specific unary operations */
-uint64_t do_float_recip_d(uint64_t fdt0)
+uint64_t helper_float_recip_d(uint64_t fdt0)
 {
     uint64_t fdt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
     update_fcr31();
     return fdt2;
 }
 
-uint32_t do_float_recip_s(uint32_t fst0)
+uint32_t helper_float_recip_s(uint32_t fst0)
 {
     uint32_t fst2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_div(FLOAT_ONE32, fst0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
     update_fcr31();
     return fst2;
 }
 
-uint64_t do_float_rsqrt_d(uint64_t fdt0)
+uint64_t helper_float_rsqrt_d(uint64_t fdt0)
 {
     uint64_t fdt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = float64_sqrt(fdt0, &env->fpu->fp_status);
-    fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
+    fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
     update_fcr31();
     return fdt2;
 }
 
-uint32_t do_float_rsqrt_s(uint32_t fst0)
+uint32_t helper_float_rsqrt_s(uint32_t fst0)
 {
     uint32_t fst2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_sqrt(fst0, &env->fpu->fp_status);
-    fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
+    fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
     update_fcr31();
     return fst2;
 }
 
-uint64_t do_float_recip1_d(uint64_t fdt0)
+uint64_t helper_float_recip1_d(uint64_t fdt0)
 {
     uint64_t fdt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
     update_fcr31();
     return fdt2;
 }
 
-uint32_t do_float_recip1_s(uint32_t fst0)
+uint32_t helper_float_recip1_s(uint32_t fst0)
 {
     uint32_t fst2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_div(FLOAT_ONE32, fst0, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
     update_fcr31();
     return fst2;
 }
 
-uint64_t do_float_recip1_ps(uint64_t fdt0)
+uint64_t helper_float_recip1_ps(uint64_t fdt0)
 {
     uint32_t fst2;
     uint32_t fsth2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);
-    fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+    fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
     update_fcr31();
     return ((uint64_t)fsth2 << 32) | fst2;
 }
 
-uint64_t do_float_rsqrt1_d(uint64_t fdt0)
+uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
 {
     uint64_t fdt2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = float64_sqrt(fdt0, &env->fpu->fp_status);
-    fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
+    fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
     update_fcr31();
     return fdt2;
 }
 
-uint32_t do_float_rsqrt1_s(uint32_t fst0)
+uint32_t helper_float_rsqrt1_s(uint32_t fst0)
 {
     uint32_t fst2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_sqrt(fst0, &env->fpu->fp_status);
-    fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
+    fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
     update_fcr31();
     return fst2;
 }
 
-uint64_t do_float_rsqrt1_ps(uint64_t fdt0)
+uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
 {
     uint32_t fst2;
     uint32_t fsth2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->fpu->fp_status);
-    fsth2 = float32_sqrt(fdt0 >> 32, &env->fpu->fp_status);
-    fst2 = float32_div(FLOAT_ONE32, fst2, &env->fpu->fp_status);
-    fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+    fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
+    fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
+    fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
     update_fcr31();
     return ((uint64_t)fsth2 << 32) | fst2;
 }
 
-#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
+#define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
 
 /* binary operations */
 #define FLOAT_BINOP(name)                                          \
-uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1)     \
+uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1)     \
 {                                                                  \
     uint64_t dt2;                                                  \
                                                                    \
-    set_float_exception_flags(0, &env->fpu->fp_status);            \
-    dt2 = float64_ ## name (fdt0, fdt1, &env->fpu->fp_status);     \
+    set_float_exception_flags(0, &env->active_fpu.fp_status);            \
+    dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
     update_fcr31();                                                \
-    if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID)                \
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
         dt2 = FLOAT_QNAN64;                                        \
     return dt2;                                                    \
 }                                                                  \
                                                                    \
-uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1)     \
+uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1)     \
 {                                                                  \
     uint32_t wt2;                                                  \
                                                                    \
-    set_float_exception_flags(0, &env->fpu->fp_status);            \
-    wt2 = float32_ ## name (fst0, fst1, &env->fpu->fp_status);     \
+    set_float_exception_flags(0, &env->active_fpu.fp_status);            \
+    wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
     update_fcr31();                                                \
-    if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID)                \
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
         wt2 = FLOAT_QNAN32;                                        \
     return wt2;                                                    \
 }                                                                  \
                                                                    \
-uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1)    \
+uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1)    \
 {                                                                  \
     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
     uint32_t fsth0 = fdt0 >> 32;                                   \
@@ -2574,11 +2515,11 @@ uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1)    \
     uint32_t wt2;                                                  \
     uint32_t wth2;                                                 \
                                                                    \
-    set_float_exception_flags(0, &env->fpu->fp_status);            \
-    wt2 = float32_ ## name (fst0, fst1, &env->fpu->fp_status);     \
-    wth2 = float32_ ## name (fsth0, fsth1, &env->fpu->fp_status);  \
+    set_float_exception_flags(0, &env->active_fpu.fp_status);            \
+    wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
+    wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
     update_fcr31();                                                \
-    if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) {              \
+    if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {              \
         wt2 = FLOAT_QNAN32;                                        \
         wth2 = FLOAT_QNAN32;                                       \
     }                                                              \
@@ -2593,21 +2534,21 @@ FLOAT_BINOP(div)
 
 /* ternary operations */
 #define FLOAT_TERNOP(name1, name2)                                        \
-uint64_t do_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1,  \
+uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1,  \
                                            uint64_t fdt2)                 \
 {                                                                         \
-    fdt0 = float64_ ## name1 (fdt0, fdt1, &env->fpu->fp_status);          \
-    return float64_ ## name2 (fdt0, fdt2, &env->fpu->fp_status);          \
+    fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
+    return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
 }                                                                         \
                                                                           \
-uint32_t do_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1,  \
+uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1,  \
                                            uint32_t fst2)                 \
 {                                                                         \
-    fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status);          \
-    return float32_ ## name2 (fst0, fst2, &env->fpu->fp_status);          \
+    fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
+    return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
 }                                                                         \
                                                                           \
-uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
+uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
                                             uint64_t fdt2)                \
 {                                                                         \
     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
@@ -2617,10 +2558,10 @@ uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
     uint32_t fsth2 = fdt2 >> 32;                                          \
                                                                           \
-    fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status);          \
-    fsth0 = float32_ ## name1 (fsth0, fsth1, &env->fpu->fp_status);       \
-    fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status);          \
-    fsth2 = float32_ ## name2 (fsth0, fsth2, &env->fpu->fp_status);       \
+    fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
+    fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
+    fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
+    fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
     return ((uint64_t)fsth2 << 32) | fst2;                                \
 }
 
@@ -2630,23 +2571,23 @@ FLOAT_TERNOP(mul, sub)
 
 /* negated ternary operations */
 #define FLOAT_NTERNOP(name1, name2)                                       \
-uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
+uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
                                            uint64_t fdt2)                 \
 {                                                                         \
-    fdt0 = float64_ ## name1 (fdt0, fdt1, &env->fpu->fp_status);          \
-    fdt2 = float64_ ## name2 (fdt0, fdt2, &env->fpu->fp_status);          \
+    fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
+    fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
     return float64_chs(fdt2);                                             \
 }                                                                         \
                                                                           \
-uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
+uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
                                            uint32_t fst2)                 \
 {                                                                         \
-    fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status);          \
-    fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status);          \
+    fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
+    fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
     return float32_chs(fst2);                                             \
 }                                                                         \
                                                                           \
-uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
+uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
                                            uint64_t fdt2)                 \
 {                                                                         \
     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
@@ -2656,10 +2597,10 @@ uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
     uint32_t fsth2 = fdt2 >> 32;                                          \
                                                                           \
-    fst0 = float32_ ## name1 (fst0, fst1, &env->fpu->fp_status);          \
-    fsth0 = float32_ ## name1 (fsth0, fsth1, &env->fpu->fp_status);       \
-    fst2 = float32_ ## name2 (fst0, fst2, &env->fpu->fp_status);          \
-    fsth2 = float32_ ## name2 (fsth0, fsth2, &env->fpu->fp_status);       \
+    fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
+    fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
+    fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
+    fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
     fst2 = float32_chs(fst2);                                             \
     fsth2 = float32_chs(fsth2);                                           \
     return ((uint64_t)fsth2 << 32) | fst2;                                \
@@ -2670,79 +2611,79 @@ FLOAT_NTERNOP(mul, sub)
 #undef FLOAT_NTERNOP
 
 /* MIPS specific binary operations */
-uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
 {
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = float64_mul(fdt0, fdt2, &env->fpu->fp_status);
-    fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->fpu->fp_status));
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
+    fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
     update_fcr31();
     return fdt2;
 }
 
-uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2)
+uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
 {
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
-    fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status));
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+    fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
     update_fcr31();
     return fst2;
 }
 
-uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
 {
     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
     uint32_t fsth0 = fdt0 >> 32;
     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
     uint32_t fsth2 = fdt2 >> 32;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
-    fsth2 = float32_mul(fsth0, fsth2, &env->fpu->fp_status);
-    fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status));
-    fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->fpu->fp_status));
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+    fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
+    fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
+    fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
     update_fcr31();
     return ((uint64_t)fsth2 << 32) | fst2;
 }
 
-uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
 {
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fdt2 = float64_mul(fdt0, fdt2, &env->fpu->fp_status);
-    fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->fpu->fp_status);
-    fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->fpu->fp_status));
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
+    fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
+    fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
     update_fcr31();
     return fdt2;
 }
 
-uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
+uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
 {
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
-    fst2 = float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status);
-    fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->fpu->fp_status));
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+    fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
+    fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
     update_fcr31();
     return fst2;
 }
 
-uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
 {
     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
     uint32_t fsth0 = fdt0 >> 32;
     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
     uint32_t fsth2 = fdt2 >> 32;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_mul(fst0, fst2, &env->fpu->fp_status);
-    fsth2 = float32_mul(fsth0, fsth2, &env->fpu->fp_status);
-    fst2 = float32_sub(fst2, FLOAT_ONE32, &env->fpu->fp_status);
-    fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->fpu->fp_status);
-    fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->fpu->fp_status));
-    fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->fpu->fp_status));
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+    fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
+    fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
+    fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
+    fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
+    fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
     update_fcr31();
     return ((uint64_t)fsth2 << 32) | fst2;
 }
 
-uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
+uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
 {
     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
     uint32_t fsth0 = fdt0 >> 32;
@@ -2751,14 +2692,14 @@ uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
     uint32_t fst2;
     uint32_t fsth2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_add (fst0, fsth0, &env->fpu->fp_status);
-    fsth2 = float32_add (fst1, fsth1, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
+    fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
     update_fcr31();
     return ((uint64_t)fsth2 << 32) | fst2;
 }
 
-uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
+uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
 {
     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
     uint32_t fsth0 = fdt0 >> 32;
@@ -2767,25 +2708,25 @@ uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
     uint32_t fst2;
     uint32_t fsth2;
 
-    set_float_exception_flags(0, &env->fpu->fp_status);
-    fst2 = float32_mul (fst0, fsth0, &env->fpu->fp_status);
-    fsth2 = float32_mul (fst1, fsth1, &env->fpu->fp_status);
+    set_float_exception_flags(0, &env->active_fpu.fp_status);
+    fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
+    fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
     update_fcr31();
     return ((uint64_t)fsth2 << 32) | fst2;
 }
 
 /* compare operations */
 #define FOP_COND_D(op, cond)                                   \
-void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
+void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
 {                                                              \
     int c = cond;                                              \
     update_fcr31();                                            \
     if (c)                                                     \
-        SET_FP_COND(cc, env->fpu);                             \
+        SET_FP_COND(cc, env->active_fpu);                      \
     else                                                       \
-        CLEAR_FP_COND(cc, env->fpu);                           \
+        CLEAR_FP_COND(cc, env->active_fpu);                    \
 }                                                              \
-void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
+void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
 {                                                              \
     int c;                                                     \
     fdt0 = float64_abs(fdt0);                                  \
@@ -2793,12 +2734,12 @@ void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
     c = cond;                                                  \
     update_fcr31();                                            \
     if (c)                                                     \
-        SET_FP_COND(cc, env->fpu);                             \
+        SET_FP_COND(cc, env->active_fpu);                      \
     else                                                       \
-        CLEAR_FP_COND(cc, env->fpu);                           \
+        CLEAR_FP_COND(cc, env->active_fpu);                    \
 }
 
-int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
+static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
 {
     if (float64_is_signaling_nan(a) ||
         float64_is_signaling_nan(b) ||
@@ -2814,36 +2755,36 @@ int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
 
 /* NOTE: the comma operator will make "cond" to eval to false,
  * but float*_is_unordered() is still called. */
-FOP_COND_D(f,   (float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status), 0))
-FOP_COND_D(un,  float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status))
-FOP_COND_D(eq,  !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_eq(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status)  || float64_eq(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_lt(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status)  || float64_lt(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status) && float64_le(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->fpu->fp_status)  || float64_le(fdt0, fdt1, &env->fpu->fp_status))
+FOP_COND_D(f,   (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
+FOP_COND_D(un,  float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
+FOP_COND_D(eq,  !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
 /* NOTE: the comma operator will make "cond" to eval to false,
  * but float*_is_unordered() is still called. */
-FOP_COND_D(sf,  (float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status), 0))
-FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status))
-FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_eq(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status)  || float64_eq(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(lt,  !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_lt(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status)  || float64_lt(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(le,  !float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status) && float64_le(fdt0, fdt1, &env->fpu->fp_status))
-FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->fpu->fp_status)  || float64_le(fdt0, fdt1, &env->fpu->fp_status))
+FOP_COND_D(sf,  (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
+FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
+FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(lt,  !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(le,  !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
+FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
 
 #define FOP_COND_S(op, cond)                                   \
-void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc)    \
+void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc)    \
 {                                                              \
     int c = cond;                                              \
     update_fcr31();                                            \
     if (c)                                                     \
-        SET_FP_COND(cc, env->fpu);                             \
+        SET_FP_COND(cc, env->active_fpu);                      \
     else                                                       \
-        CLEAR_FP_COND(cc, env->fpu);                           \
+        CLEAR_FP_COND(cc, env->active_fpu);                    \
 }                                                              \
-void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
+void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
 {                                                              \
     int c;                                                     \
     fst0 = float32_abs(fst0);                                  \
@@ -2851,12 +2792,12 @@ void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
     c = cond;                                                  \
     update_fcr31();                                            \
     if (c)                                                     \
-        SET_FP_COND(cc, env->fpu);                             \
+        SET_FP_COND(cc, env->active_fpu);                      \
     else                                                       \
-        CLEAR_FP_COND(cc, env->fpu);                           \
+        CLEAR_FP_COND(cc, env->active_fpu);                    \
 }
 
-flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
+static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
 {
     if (float32_is_signaling_nan(a) ||
         float32_is_signaling_nan(b) ||
@@ -2872,27 +2813,27 @@ flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
 
 /* NOTE: the comma operator will make "cond" to eval to false,
  * but float*_is_unordered() is still called. */
-FOP_COND_S(f,   (float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status), 0))
-FOP_COND_S(un,  float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status))
-FOP_COND_S(eq,  !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)  || float32_eq(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)  || float32_lt(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)  || float32_le(fst0, fst1, &env->fpu->fp_status))
+FOP_COND_S(f,   (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
+FOP_COND_S(un,  float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
+FOP_COND_S(eq,  !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
 /* NOTE: the comma operator will make "cond" to eval to false,
  * but float*_is_unordered() is still called. */
-FOP_COND_S(sf,  (float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status), 0))
-FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status))
-FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_eq(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)  || float32_eq(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(lt,  !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_lt(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)  || float32_lt(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(le,  !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status) && float32_le(fst0, fst1, &env->fpu->fp_status))
-FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)  || float32_le(fst0, fst1, &env->fpu->fp_status))
+FOP_COND_S(sf,  (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
+FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
+FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(lt,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(le,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
+FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
 
 #define FOP_COND_PS(op, condl, condh)                           \
-void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
+void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
 {                                                               \
     uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF);             \
     uint32_t fsth0 = float32_abs(fdt0 >> 32);                   \
@@ -2903,15 +2844,15 @@ void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
                                                                 \
     update_fcr31();                                             \
     if (cl)                                                     \
-        SET_FP_COND(cc, env->fpu);                              \
+        SET_FP_COND(cc, env->active_fpu);                       \
     else                                                        \
-        CLEAR_FP_COND(cc, env->fpu);                            \
+        CLEAR_FP_COND(cc, env->active_fpu);                     \
     if (ch)                                                     \
-        SET_FP_COND(cc + 1, env->fpu);                          \
+        SET_FP_COND(cc + 1, env->active_fpu);                   \
     else                                                        \
-        CLEAR_FP_COND(cc + 1, env->fpu);                        \
+        CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
 }                                                               \
-void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
+void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
 {                                                               \
     uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF);             \
     uint32_t fsth0 = float32_abs(fdt0 >> 32);                   \
@@ -2922,48 +2863,48 @@ void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
                                                                 \
     update_fcr31();                                             \
     if (cl)                                                     \
-        SET_FP_COND(cc, env->fpu);                              \
+        SET_FP_COND(cc, env->active_fpu);                       \
     else                                                        \
-        CLEAR_FP_COND(cc, env->fpu);                            \
+        CLEAR_FP_COND(cc, env->active_fpu);                     \
     if (ch)                                                     \
-        SET_FP_COND(cc + 1, env->fpu);                          \
+        SET_FP_COND(cc + 1, env->active_fpu);                   \
     else                                                        \
-        CLEAR_FP_COND(cc + 1, env->fpu);                        \
+        CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
 }
 
 /* NOTE: the comma operator will make "cond" to eval to false,
  * but float*_is_unordered() is still called. */
-FOP_COND_PS(f,   (float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status), 0),
-                 (float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status), 0))
-FOP_COND_PS(un,  float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status),
-                 float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status))
-FOP_COND_PS(eq,  !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)   && float32_eq(fst0, fst1, &env->fpu->fp_status),
-                 !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_eq(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)    || float32_eq(fst0, fst1, &env->fpu->fp_status),
-                 float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status)  || float32_eq(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)   && float32_lt(fst0, fst1, &env->fpu->fp_status),
-                 !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_lt(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)    || float32_lt(fst0, fst1, &env->fpu->fp_status),
-                 float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status)  || float32_lt(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)   && float32_le(fst0, fst1, &env->fpu->fp_status),
-                 !float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status) && float32_le(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->fpu->fp_status)    || float32_le(fst0, fst1, &env->fpu->fp_status),
-                 float32_is_unordered(0, fsth1, fsth0, &env->fpu->fp_status)  || float32_le(fsth0, fsth1, &env->fpu->fp_status))
+FOP_COND_PS(f,   (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
+                 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
+FOP_COND_PS(un,  float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
+                 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
+FOP_COND_PS(eq,  !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
+                 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
+                 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
+                 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
+                 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_le(fst0, fst1, &env->active_fpu.fp_status),
+                 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
+                 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
 /* NOTE: the comma operator will make "cond" to eval to false,
  * but float*_is_unordered() is still called. */
-FOP_COND_PS(sf,  (float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status), 0),
-                 (float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status), 0))
-FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status),
-                 float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status))
-FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)   && float32_eq(fst0, fst1, &env->fpu->fp_status),
-                 !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_eq(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)    || float32_eq(fst0, fst1, &env->fpu->fp_status),
-                 float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status)  || float32_eq(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(lt,  !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)   && float32_lt(fst0, fst1, &env->fpu->fp_status),
-                 !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_lt(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)    || float32_lt(fst0, fst1, &env->fpu->fp_status),
-                 float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status)  || float32_lt(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(le,  !float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)   && float32_le(fst0, fst1, &env->fpu->fp_status),
-                 !float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status) && float32_le(fsth0, fsth1, &env->fpu->fp_status))
-FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->fpu->fp_status)    || float32_le(fst0, fst1, &env->fpu->fp_status),
-                 float32_is_unordered(1, fsth1, fsth0, &env->fpu->fp_status)  || float32_le(fsth0, fsth1, &env->fpu->fp_status))
+FOP_COND_PS(sf,  (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
+                 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
+FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
+                 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
+FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
+                 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
+                 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(lt,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
+                 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
+                 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(le,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_le(fst0, fst1, &env->active_fpu.fp_status),
+                 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
+FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
+                 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))