* QEMU Sparc SLAVIO timer controller emulation
*
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* This is the timer/counter part of chip STP2001 (Slave I/O), also
* produced as NCR89C105. See
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
- *
+ *
* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
* are zero. Bit 31 is 1 when count has been reached.
*
*
*/
+#define MAX_CPUS 16
+
typedef struct SLAVIO_TIMERState {
- uint32_t limit, count, counthigh;
- int64_t count_load_time;
- int64_t expire_time;
- int64_t stop_time, tick_offset;
- QEMUTimer *irq_timer;
- int irq;
- int reached, stopped;
- int mode; // 0 = processor, 1 = user, 2 = system
- unsigned int cpu;
+ qemu_irq irq;
+ ptimer_state *timer;
+ uint32_t count, counthigh, reached;
+ uint64_t limit;
+ // processor only
+ int running;
+ struct SLAVIO_TIMERState *master;
+ int slave_index;
+ // system only
+ struct SLAVIO_TIMERState *slave[MAX_CPUS];
+ uint32_t slave_mode;
} SLAVIO_TIMERState;
#define TIMER_MAXADDR 0x1f
-#define CNT_FREQ 2000000
+#define SYS_TIMER_SIZE 0x14
+#define CPU_TIMER_SIZE 0x10
+
+static int slavio_timer_is_user(SLAVIO_TIMERState *s)
+{
+ return s->master && (s->master->slave_mode & (1 << s->slave_index));
+}
// Update count, set irq, update expire_time
+// Convert from ptimer countdown units
static void slavio_timer_get_out(SLAVIO_TIMERState *s)
{
- int out;
- int64_t diff, ticks, count;
- uint32_t limit;
-
- // There are three clock tick units: CPU ticks, register units
- // (nanoseconds), and counter ticks (500 ns).
- if (s->mode == 1 && s->stopped)
- ticks = s->stop_time;
- else
- ticks = qemu_get_clock(vm_clock) - s->tick_offset;
-
- out = (ticks > s->expire_time);
- if (out)
- s->reached = 0x80000000;
- if (!s->limit)
- limit = 0x7fffffff;
- else
- limit = s->limit;
-
- // Convert register units to counter ticks
- limit = limit >> 9;
-
- // Convert cpu ticks to counter ticks
- diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);
-
- // Calculate what the counter should be, convert to register
- // units
- count = diff % limit;
- s->count = count << 9;
- s->counthigh = count >> 22;
+ uint64_t count;
- // Expire time: CPU ticks left to next interrupt
- // Convert remaining counter ticks to CPU ticks
- s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);
-
- DPRINTF("irq %d limit %d reached %d d %lld count %d s->c %x diff %lld stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
-
- if (s->mode != 1)
- pic_set_irq_cpu(s->irq, out, s->cpu);
+ count = s->limit - (ptimer_get_count(s->timer) << 9);
+ DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
+ s->count);
+ s->count = count & 0xfffffe00;
+ s->counthigh = count >> 32;
}
// timer callback
{
SLAVIO_TIMERState *s = opaque;
- if (!s->irq_timer)
- return;
slavio_timer_get_out(s);
- if (s->mode != 1)
- qemu_mod_timer(s->irq_timer, s->expire_time);
+ DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
+ if (!slavio_timer_is_user(s)) {
+ s->reached = 0x80000000;
+ qemu_irq_raise(s->irq);
+ }
}
static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
{
SLAVIO_TIMERState *s = opaque;
- uint32_t saddr;
+ uint32_t saddr, ret;
saddr = (addr & TIMER_MAXADDR) >> 2;
switch (saddr) {
case 0:
- // read limit (system counter mode) or read most signifying
- // part of counter (user mode)
- if (s->mode != 1) {
- // clear irq
- pic_set_irq_cpu(s->irq, 0, s->cpu);
- s->count_load_time = qemu_get_clock(vm_clock);
- s->reached = 0;
- return s->limit;
- }
- else {
- slavio_timer_get_out(s);
- return s->counthigh & 0x7fffffff;
- }
+ // read limit (system counter mode) or read most signifying
+ // part of counter (user mode)
+ if (slavio_timer_is_user(s)) {
+ // read user timer MSW
+ slavio_timer_get_out(s);
+ ret = s->counthigh;
+ } else {
+ // read limit
+ // clear irq
+ qemu_irq_lower(s->irq);
+ s->reached = 0;
+ ret = s->limit & 0x7fffffff;
+ }
+ break;
case 1:
- // read counter and reached bit (system mode) or read lsbits
- // of counter (user mode)
- slavio_timer_get_out(s);
- if (s->mode != 1)
- return (s->count & 0x7fffffff) | s->reached;
- else
- return s->count;
+ // read counter and reached bit (system mode) or read lsbits
+ // of counter (user mode)
+ slavio_timer_get_out(s);
+ if (slavio_timer_is_user(s)) // read user timer LSW
+ ret = s->count & 0xffffffe00;
+ else // read limit
+ ret = (s->count & 0x7ffffe00) | s->reached;
+ break;
case 3:
- // read start/stop status
- return s->stopped;
+ // only available in processor counter/timer
+ // read start/stop status
+ ret = s->running;
+ break;
case 4:
- // read user/system mode
- return s->mode & 1;
+ // only available in system counter
+ // read user/system mode
+ ret = s->slave_mode;
+ break;
default:
- return 0;
+ DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
+ ret = 0;
+ break;
}
+ DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
+
+ return ret;
}
static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
SLAVIO_TIMERState *s = opaque;
uint32_t saddr;
+ int reload = 0;
+ DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
saddr = (addr & TIMER_MAXADDR) >> 2;
switch (saddr) {
case 0:
- // set limit, reset counter
- s->count_load_time = qemu_get_clock(vm_clock);
- // fall through
+ if (slavio_timer_is_user(s)) {
+ // set user counter MSW, reset counter
+ qemu_irq_lower(s->irq);
+ s->limit = 0x7ffffffffffffe00ULL;
+ DPRINTF("processor %d user timer reset\n", s->slave_index);
+ ptimer_set_limit(s->timer, s->limit >> 9, 1);
+ } else {
+ // set limit, reset counter
+ qemu_irq_lower(s->irq);
+ s->limit = val & 0x7ffffe00ULL;
+ if (!s->limit)
+ s->limit = 0x7ffffe00ULL;
+ ptimer_set_limit(s->timer, s->limit >> 9, 1);
+ }
+ break;
+ case 1:
+ if (slavio_timer_is_user(s)) {
+ // set user counter LSW, reset counter
+ qemu_irq_lower(s->irq);
+ s->limit = 0x7ffffffffffffe00ULL;
+ DPRINTF("processor %d user timer reset\n", s->slave_index);
+ ptimer_set_limit(s->timer, s->limit >> 9, 1);
+ } else
+ DPRINTF("not user timer\n");
+ break;
case 2:
- // set limit without resetting counter
- if (!val)
- s->limit = 0x7fffffff;
- else
- s->limit = val & 0x7fffffff;
- slavio_timer_irq(s);
- break;
+ // set limit without resetting counter
+ s->limit = val & 0x7ffffe00ULL;
+ if (!s->limit)
+ s->limit = 0x7ffffe00ULL;
+ ptimer_set_limit(s->timer, s->limit >> 9, reload);
+ break;
case 3:
- // start/stop user counter
- if (s->mode == 1) {
- if (val & 1) {
- s->stop_time = qemu_get_clock(vm_clock);
- s->stopped = 1;
- }
- else {
- if (s->stopped)
- s->tick_offset += qemu_get_clock(vm_clock) - s->stop_time;
- s->stopped = 0;
- }
- }
- break;
+ if (slavio_timer_is_user(s)) {
+ // start/stop user counter
+ if ((val & 1) && !s->running) {
+ DPRINTF("processor %d user timer started\n", s->slave_index);
+ ptimer_run(s->timer, 0);
+ s->running = 1;
+ } else if (!(val & 1) && s->running) {
+ DPRINTF("processor %d user timer stopped\n", s->slave_index);
+ ptimer_stop(s->timer);
+ s->running = 0;
+ }
+ }
+ break;
case 4:
- // bit 0: user (1) or system (0) counter mode
- if (s->mode == 0 || s->mode == 1)
- s->mode = val & 1;
- break;
+ if (s->master == NULL) {
+ unsigned int i;
+
+ for (i = 0; i < MAX_CPUS; i++) {
+ if (val & (1 << i)) {
+ qemu_irq_lower(s->slave[i]->irq);
+ s->slave[i]->limit = -1ULL;
+ }
+ if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
+ ptimer_stop(s->slave[i]->timer);
+ ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9, 1);
+ DPRINTF("processor %d timer changed\n", s->slave[i]->slave_index);
+ ptimer_run(s->slave[i]->timer, 0);
+ }
+ }
+ s->slave_mode = val & ((1 << MAX_CPUS) - 1);
+ } else
+ DPRINTF("not system timer\n");
+ break;
default:
- break;
+ DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
+ break;
}
}
{
SLAVIO_TIMERState *s = opaque;
- qemu_put_be32s(f, &s->limit);
+ qemu_put_be64s(f, &s->limit);
qemu_put_be32s(f, &s->count);
qemu_put_be32s(f, &s->counthigh);
- qemu_put_be64s(f, &s->count_load_time);
- qemu_put_be64s(f, &s->expire_time);
- qemu_put_be64s(f, &s->stop_time);
- qemu_put_be64s(f, &s->tick_offset);
- qemu_put_be32s(f, &s->irq);
+ qemu_put_be32(f, 0); // Was irq
qemu_put_be32s(f, &s->reached);
- qemu_put_be32s(f, &s->stopped);
- qemu_put_be32s(f, &s->mode);
+ qemu_put_be32s(f, &s->running);
+ qemu_put_be32s(f, 0); // Was mode
+ qemu_put_ptimer(f, s->timer);
}
static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
{
SLAVIO_TIMERState *s = opaque;
-
- if (version_id != 1)
+ uint32_t tmp;
+
+ if (version_id != 2)
return -EINVAL;
- qemu_get_be32s(f, &s->limit);
+ qemu_get_be64s(f, &s->limit);
qemu_get_be32s(f, &s->count);
qemu_get_be32s(f, &s->counthigh);
- qemu_get_be64s(f, &s->count_load_time);
- qemu_get_be64s(f, &s->expire_time);
- qemu_get_be64s(f, &s->stop_time);
- qemu_get_be64s(f, &s->tick_offset);
- qemu_get_be32s(f, &s->irq);
+ qemu_get_be32s(f, &tmp); // Was irq
qemu_get_be32s(f, &s->reached);
- qemu_get_be32s(f, &s->stopped);
- qemu_get_be32s(f, &s->mode);
+ qemu_get_be32s(f, &s->running);
+ qemu_get_be32s(f, &tmp); // Was mode
+ qemu_get_ptimer(f, s->timer);
+
return 0;
}
{
SLAVIO_TIMERState *s = opaque;
- s->limit = 0;
+ if (slavio_timer_is_user(s))
+ s->limit = 0x7ffffffffffffe00ULL;
+ else
+ s->limit = 0x7ffffe00ULL;
s->count = 0;
- s->count_load_time = qemu_get_clock(vm_clock);;
- s->stop_time = s->count_load_time;
- s->tick_offset = 0;
s->reached = 0;
- s->mode &= 2;
- s->stopped = 1;
- slavio_timer_get_out(s);
+ ptimer_set_limit(s->timer, s->limit >> 9, 1);
+ ptimer_run(s->timer, 0);
+ s->running = 1;
+ qemu_irq_lower(s->irq);
}
-void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu)
+static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
+ qemu_irq irq,
+ SLAVIO_TIMERState *master,
+ int slave_index)
{
int slavio_timer_io_memory;
SLAVIO_TIMERState *s;
+ QEMUBH *bh;
s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
if (!s)
- return;
+ return s;
s->irq = irq;
- s->mode = mode;
- s->cpu = cpu;
- s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
+ s->master = master;
+ s->slave_index = slave_index;
+ bh = qemu_bh_new(slavio_timer_irq, s);
+ s->timer = ptimer_init(bh);
+ ptimer_set_period(s->timer, 500ULL);
slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
- slavio_timer_mem_write, s);
- cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
- register_savevm("slavio_timer", addr, 1, slavio_timer_save, slavio_timer_load, s);
+ slavio_timer_mem_write, s);
+ if (master)
+ cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
+ else
+ cpu_register_physical_memory(addr, SYS_TIMER_SIZE, slavio_timer_io_memory);
+ register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
qemu_register_reset(slavio_timer_reset, s);
slavio_timer_reset(s);
+
+ return s;
+}
+
+void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
+ qemu_irq *cpu_irqs)
+{
+ SLAVIO_TIMERState *master;
+ unsigned int i;
+
+ master = slavio_timer_init(base + 0x10000ULL, master_irq, NULL, 0);
+
+ for (i = 0; i < MAX_CPUS; i++) {
+ master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
+ (i * TARGET_PAGE_SIZE),
+ cpu_irqs[i], master, i);
+ }
}
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