#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "qemu-common.h"
#include "cpu.h"
-#include "hw/hw.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/xics.h"
+#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
+#include "qemu/module.h"
#include "qapi/visitor.h"
+#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
+#include "hw/irq.h"
+#include "sysemu/kvm.h"
+#include "sysemu/reset.h"
void icp_pic_print_info(ICPState *icp, Monitor *mon)
{
- ICPStateClass *icpc = ICP_GET_CLASS(icp);
int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
if (!icp->output) {
return;
}
- if (icpc->synchronize_state) {
- icpc->synchronize_state(icp);
+ if (kvm_irqchip_in_kernel()) {
+ icp_synchronize_state(icp);
}
monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
void ics_pic_print_info(ICSState *ics, Monitor *mon)
{
- ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
uint32_t i;
monitor_printf(mon, "ICS %4x..%4x %p\n",
return;
}
- if (icsc->synchronize_state) {
- icsc->synchronize_state(ics);
+ if (kvm_irqchip_in_kernel()) {
+ ics_synchronize_state(ics);
}
for (i = 0; i < ics->nr_irqs; i++) {
#define XISR(icp) (((icp)->xirr) & XISR_MASK)
#define CPPR(icp) (((icp)->xirr) >> 24)
-static void ics_reject(ICSState *ics, uint32_t nr)
-{
- ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
-
- if (k->reject) {
- k->reject(ics, nr);
- }
-}
-
-void ics_resend(ICSState *ics)
-{
- ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
-
- if (k->resend) {
- k->resend(ics);
- }
-}
-
-static void ics_eoi(ICSState *ics, int nr)
-{
- ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
-
- if (k->eoi) {
- k->eoi(ics, nr);
- }
-}
+static void ics_reject(ICSState *ics, uint32_t nr);
+static void ics_eoi(ICSState *ics, uint32_t nr);
static void icp_check_ipi(ICPState *icp)
{
}
}
-static int icp_dispatch_pre_save(void *opaque)
+static int icp_pre_save(void *opaque)
{
ICPState *icp = opaque;
- ICPStateClass *info = ICP_GET_CLASS(icp);
- if (info->pre_save) {
- info->pre_save(icp);
+ if (kvm_irqchip_in_kernel()) {
+ icp_get_kvm_state(icp);
}
return 0;
}
-static int icp_dispatch_post_load(void *opaque, int version_id)
+static int icp_post_load(void *opaque, int version_id)
{
ICPState *icp = opaque;
- ICPStateClass *info = ICP_GET_CLASS(icp);
- if (info->post_load) {
- return info->post_load(icp, version_id);
+ if (kvm_irqchip_in_kernel()) {
+ Error *local_err = NULL;
+ int ret;
+
+ ret = icp_set_kvm_state(icp, &local_err);
+ if (ret < 0) {
+ error_report_err(local_err);
+ return ret;
+ }
}
return 0;
.name = "icp/server",
.version_id = 1,
.minimum_version_id = 1,
- .pre_save = icp_dispatch_pre_save,
- .post_load = icp_dispatch_post_load,
+ .pre_save = icp_pre_save,
+ .post_load = icp_post_load,
.fields = (VMStateField[]) {
/* Sanity check */
VMSTATE_UINT32(xirr, ICPState),
},
};
-static void icp_reset(DeviceState *dev)
+static void icp_reset_handler(void *dev)
{
ICPState *icp = ICP(dev);
/* Make all outputs are deasserted */
qemu_set_irq(icp->output, 0);
-}
-static void icp_reset_handler(void *dev)
-{
- DeviceClass *dc = DEVICE_GET_CLASS(dev);
+ if (kvm_irqchip_in_kernel()) {
+ Error *local_err = NULL;
- dc->reset(dev);
+ icp_set_kvm_state(ICP(dev), &local_err);
+ if (local_err) {
+ error_report_err(local_err);
+ }
+ }
}
static void icp_realize(DeviceState *dev, Error **errp)
obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
if (!obj) {
- error_propagate(errp, err);
- error_prepend(errp, "required link '" ICP_PROP_XICS "' not found: ");
+ error_propagate_prepend(errp, err,
+ "required link '" ICP_PROP_XICS
+ "' not found: ");
return;
}
obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
if (!obj) {
- error_propagate(errp, err);
- error_prepend(errp, "required link '" ICP_PROP_CPU "' not found: ");
+ error_propagate_prepend(errp, err,
+ "required link '" ICP_PROP_CPU
+ "' not found: ");
return;
}
case PPC_FLAGS_INPUT_POWER7:
icp->output = env->irq_inputs[POWER7_INPUT_INT];
break;
+ case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
+ icp->output = env->irq_inputs[POWER9_INPUT_INT];
+ break;
case PPC_FLAGS_INPUT_970:
icp->output = env->irq_inputs[PPC970_INPUT_INT];
return;
}
+ /* Connect the presenter to the VCPU (required for CPU hotplug) */
+ if (kvm_irqchip_in_kernel()) {
+ icp_kvm_realize(dev, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ }
+
qemu_register_reset(icp_reset_handler, dev);
vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
}
dc->realize = icp_realize;
dc->unrealize = icp_unrealize;
- dc->reset = icp_reset;
}
static const TypeInfo icp_info = {
/*
* ICS: Source layer
*/
-static void ics_simple_resend_msi(ICSState *ics, int srcno)
+static void ics_resend_msi(ICSState *ics, int srcno)
{
ICSIRQState *irq = ics->irqs + srcno;
}
}
-static void ics_simple_resend_lsi(ICSState *ics, int srcno)
+static void ics_resend_lsi(ICSState *ics, int srcno)
{
ICSIRQState *irq = ics->irqs + srcno;
}
}
-static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
+static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
{
ICSIRQState *irq = ics->irqs + srcno;
- trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
+ trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
if (val) {
if (irq->priority == 0xff) {
}
}
-static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
+static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
{
ICSIRQState *irq = ics->irqs + srcno;
- trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
+ trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
if (val) {
irq->status |= XICS_STATUS_ASSERTED;
} else {
irq->status &= ~XICS_STATUS_ASSERTED;
}
- ics_simple_resend_lsi(ics, srcno);
+ ics_resend_lsi(ics, srcno);
}
-static void ics_simple_set_irq(void *opaque, int srcno, int val)
+void ics_set_irq(void *opaque, int srcno, int val)
{
ICSState *ics = (ICSState *)opaque;
+ if (kvm_irqchip_in_kernel()) {
+ ics_kvm_set_irq(ics, srcno, val);
+ return;
+ }
+
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
- ics_simple_set_irq_lsi(ics, srcno, val);
+ ics_set_irq_lsi(ics, srcno, val);
} else {
- ics_simple_set_irq_msi(ics, srcno, val);
+ ics_set_irq_msi(ics, srcno, val);
}
}
-static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
+static void ics_write_xive_msi(ICSState *ics, int srcno)
{
ICSIRQState *irq = ics->irqs + srcno;
icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
}
-static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
+static void ics_write_xive_lsi(ICSState *ics, int srcno)
{
- ics_simple_resend_lsi(ics, srcno);
+ ics_resend_lsi(ics, srcno);
}
-void ics_simple_write_xive(ICSState *ics, int srcno, int server,
- uint8_t priority, uint8_t saved_priority)
+void ics_write_xive(ICSState *ics, int srcno, int server,
+ uint8_t priority, uint8_t saved_priority)
{
ICSIRQState *irq = ics->irqs + srcno;
irq->priority = priority;
irq->saved_priority = saved_priority;
- trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
- priority);
+ trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
- ics_simple_write_xive_lsi(ics, srcno);
+ ics_write_xive_lsi(ics, srcno);
} else {
- ics_simple_write_xive_msi(ics, srcno);
+ ics_write_xive_msi(ics, srcno);
}
}
-static void ics_simple_reject(ICSState *ics, uint32_t nr)
+static void ics_reject(ICSState *ics, uint32_t nr)
{
ICSIRQState *irq = ics->irqs + nr - ics->offset;
- trace_xics_ics_simple_reject(nr, nr - ics->offset);
+ trace_xics_ics_reject(nr, nr - ics->offset);
if (irq->flags & XICS_FLAGS_IRQ_MSI) {
irq->status |= XICS_STATUS_REJECTED;
} else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
}
}
-static void ics_simple_resend(ICSState *ics)
+void ics_resend(ICSState *ics)
{
int i;
for (i = 0; i < ics->nr_irqs; i++) {
/* FIXME: filter by server#? */
if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
- ics_simple_resend_lsi(ics, i);
+ ics_resend_lsi(ics, i);
} else {
- ics_simple_resend_msi(ics, i);
+ ics_resend_msi(ics, i);
}
}
}
-static void ics_simple_eoi(ICSState *ics, uint32_t nr)
+static void ics_eoi(ICSState *ics, uint32_t nr)
{
int srcno = nr - ics->offset;
ICSIRQState *irq = ics->irqs + srcno;
- trace_xics_ics_simple_eoi(nr);
+ trace_xics_ics_eoi(nr);
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
irq->status &= ~XICS_STATUS_SENT;
}
}
-static void ics_simple_reset(DeviceState *dev)
-{
- ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
-
- icsc->parent_reset(dev);
-}
-
-static void ics_simple_reset_handler(void *dev)
-{
- ics_simple_reset(dev);
-}
-
-static void ics_simple_realize(DeviceState *dev, Error **errp)
-{
- ICSState *ics = ICS_SIMPLE(dev);
- ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
- Error *local_err = NULL;
-
- icsc->parent_realize(dev, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
-
- ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
-
- qemu_register_reset(ics_simple_reset_handler, ics);
-}
-
-static void ics_simple_class_init(ObjectClass *klass, void *data)
+static void ics_reset_irq(ICSIRQState *irq)
{
- DeviceClass *dc = DEVICE_CLASS(klass);
- ICSStateClass *isc = ICS_BASE_CLASS(klass);
-
- device_class_set_parent_realize(dc, ics_simple_realize,
- &isc->parent_realize);
- device_class_set_parent_reset(dc, ics_simple_reset,
- &isc->parent_reset);
-
- isc->reject = ics_simple_reject;
- isc->resend = ics_simple_resend;
- isc->eoi = ics_simple_eoi;
+ irq->priority = 0xff;
+ irq->saved_priority = 0xff;
}
-static const TypeInfo ics_simple_info = {
- .name = TYPE_ICS_SIMPLE,
- .parent = TYPE_ICS_BASE,
- .instance_size = sizeof(ICSState),
- .class_init = ics_simple_class_init,
- .class_size = sizeof(ICSStateClass),
-};
-
-static void ics_base_reset(DeviceState *dev)
+static void ics_reset(DeviceState *dev)
{
- ICSState *ics = ICS_BASE(dev);
+ ICSState *ics = ICS(dev);
int i;
uint8_t flags[ics->nr_irqs];
memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
for (i = 0; i < ics->nr_irqs; i++) {
- ics->irqs[i].priority = 0xff;
- ics->irqs[i].saved_priority = 0xff;
+ ics_reset_irq(ics->irqs + i);
ics->irqs[i].flags = flags[i];
}
+
+ if (kvm_irqchip_in_kernel()) {
+ Error *local_err = NULL;
+
+ ics_set_kvm_state(ICS(dev), &local_err);
+ if (local_err) {
+ error_report_err(local_err);
+ }
+ }
+}
+
+static void ics_reset_handler(void *dev)
+{
+ ics_reset(dev);
}
-static void ics_base_realize(DeviceState *dev, Error **errp)
+static void ics_realize(DeviceState *dev, Error **errp)
{
- ICSState *ics = ICS_BASE(dev);
+ ICSState *ics = ICS(dev);
+ Error *local_err = NULL;
Object *obj;
- Error *err = NULL;
- obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
+ obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err);
if (!obj) {
- error_propagate(errp, err);
- error_prepend(errp, "required link '" ICS_PROP_XICS "' not found: ");
+ error_propagate_prepend(errp, local_err,
+ "required link '" ICS_PROP_XICS
+ "' not found: ");
return;
}
ics->xics = XICS_FABRIC(obj);
return;
}
ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
+
+ qemu_register_reset(ics_reset_handler, ics);
}
-static void ics_base_instance_init(Object *obj)
+static void ics_instance_init(Object *obj)
{
- ICSState *ics = ICS_BASE(obj);
+ ICSState *ics = ICS(obj);
ics->offset = XICS_IRQ_BASE;
}
-static int ics_base_dispatch_pre_save(void *opaque)
+static int ics_pre_save(void *opaque)
{
ICSState *ics = opaque;
- ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
- if (info->pre_save) {
- info->pre_save(ics);
+ if (kvm_irqchip_in_kernel()) {
+ ics_get_kvm_state(ics);
}
return 0;
}
-static int ics_base_dispatch_post_load(void *opaque, int version_id)
+static int ics_post_load(void *opaque, int version_id)
{
ICSState *ics = opaque;
- ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
- if (info->post_load) {
- return info->post_load(ics, version_id);
+ if (kvm_irqchip_in_kernel()) {
+ Error *local_err = NULL;
+ int ret;
+
+ ret = ics_set_kvm_state(ics, &local_err);
+ if (ret < 0) {
+ error_report_err(local_err);
+ return ret;
+ }
}
return 0;
}
-static const VMStateDescription vmstate_ics_base_irq = {
+static const VMStateDescription vmstate_ics_irq = {
.name = "ics/irq",
.version_id = 2,
.minimum_version_id = 1,
},
};
-static const VMStateDescription vmstate_ics_base = {
+static const VMStateDescription vmstate_ics = {
.name = "ics",
.version_id = 1,
.minimum_version_id = 1,
- .pre_save = ics_base_dispatch_pre_save,
- .post_load = ics_base_dispatch_post_load,
+ .pre_save = ics_pre_save,
+ .post_load = ics_post_load,
.fields = (VMStateField[]) {
/* Sanity check */
VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
- vmstate_ics_base_irq,
+ vmstate_ics_irq,
ICSIRQState),
VMSTATE_END_OF_LIST()
},
};
-static Property ics_base_properties[] = {
+static Property ics_properties[] = {
DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
DEFINE_PROP_END_OF_LIST(),
};
-static void ics_base_class_init(ObjectClass *klass, void *data)
+static void ics_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->realize = ics_base_realize;
- dc->props = ics_base_properties;
- dc->reset = ics_base_reset;
- dc->vmsd = &vmstate_ics_base;
+ dc->realize = ics_realize;
+ dc->props = ics_properties;
+ dc->reset = ics_reset;
+ dc->vmsd = &vmstate_ics;
}
-static const TypeInfo ics_base_info = {
- .name = TYPE_ICS_BASE,
+static const TypeInfo ics_info = {
+ .name = TYPE_ICS,
.parent = TYPE_DEVICE,
- .abstract = true,
.instance_size = sizeof(ICSState),
- .instance_init = ics_base_instance_init,
- .class_init = ics_base_class_init,
+ .instance_init = ics_instance_init,
+ .class_init = ics_class_init,
.class_size = sizeof(ICSStateClass),
};
ics->irqs[srcno].flags |=
lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
+
+ if (kvm_irqchip_in_kernel()) {
+ Error *local_err = NULL;
+
+ ics_reset_irq(ics->irqs + srcno);
+ ics_set_kvm_state_one(ics, srcno, &local_err);
+ if (local_err) {
+ error_report_err(local_err);
+ }
+ }
}
static void xics_register_types(void)
{
- type_register_static(&ics_simple_info);
- type_register_static(&ics_base_info);
+ type_register_static(&ics_info);
type_register_static(&icp_info);
type_register_static(&xics_fabric_info);
}
projects / qemu.git / blobdiff