#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "qemu-common.h"
#include "hw/hw.h"
#include "hw/block/flash.h"
#include "hw/irq.h"
#include "sysemu/block-backend.h"
-#include "sysemu/blockdev.h"
#include "exec/memory.h"
-#include "exec/address-spaces.h"
#include "hw/sysbus.h"
#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
}
-static void onenand_pre_save(void *opaque)
+static int onenand_pre_save(void *opaque)
{
OneNANDState *s = opaque;
if (s->current == s->otp) {
} else {
s->current_direction = 0;
}
+
+ return 0;
}
static int onenand_post_load(void *opaque, int version_id)
s->intstatus |= ONEN_INT;
for (b = 0; b < s->blocks; b ++) {
- if (b >= s->blocks) {
- s->status |= ONEN_ERR_CMD;
- break;
- }
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
break;
default:
s->status |= ONEN_ERR_CMD;
s->intstatus |= ONEN_INT;
- fprintf(stderr, "%s: unknown OneNAND command %x\n",
- __func__, s->command);
+ qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n",
+ s->command);
}
onenand_intr_update(s);
int offset = addr >> s->shift;
switch (offset) {
- case 0x0000 ... 0xc000:
+ case 0x0000 ... 0xbffe:
return lduw_le_p(s->boot[0] + addr);
case 0xf000: /* Manufacturer ID */
case 0xff02: /* ECC Result of spare area data */
case 0xff03: /* ECC Result of main area data */
case 0xff04: /* ECC Result of spare area data */
- hw_error("%s: imeplement ECC\n", __FUNCTION__);
+ qemu_log_mask(LOG_UNIMP,
+ "onenand: ECC result registers unimplemented\n");
return 0x0000;
}
- fprintf(stderr, "%s: unknown OneNAND register %x\n",
- __FUNCTION__, offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n",
+ offset);
return 0;
}
break;
default:
- fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
- __FUNCTION__, value);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "unknown OneNAND boot command %" PRIx64 "\n",
+ value);
}
break;
break;
default:
- fprintf(stderr, "%s: unknown OneNAND register %x\n",
- __FUNCTION__, offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "write to unknown OneNAND register 0x%x\n",
+ offset);
}
}
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int onenand_initfn(SysBusDevice *sbd)
+static void onenand_realize(DeviceState *dev, Error **errp)
{
- DeviceState *dev = DEVICE(sbd);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
OneNANDState *s = ONE_NAND(dev);
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
void *ram;
0xff, size + (size >> 5));
} else {
if (blk_is_read_only(s->blk)) {
- error_report("Can't use a read-only drive");
- return -1;
+ error_setg(errp, "Can't use a read-only drive");
+ return;
}
blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
BLK_PERM_ALL, &local_err);
if (local_err) {
- error_report_err(local_err);
- return -1;
+ error_propagate(errp, local_err);
+ return;
}
s->blk_cur = s->blk;
}
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
- memory_region_init_ram(&s->ram, OBJECT(s), "onenand.ram",
+ memory_region_init_ram_nomigrate(&s->ram, OBJECT(s), "onenand.ram",
0xc000 << s->shift, &error_fatal);
vmstate_register_ram_global(&s->ram);
ram = memory_region_get_ram_ptr(&s->ram);
| ((s->id.dev & 0xff) << 8)
| (s->id.ver & 0xff),
&vmstate_onenand, s);
- return 0;
}
static Property onenand_properties[] = {
static void onenand_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = onenand_initfn;
+ dc->realize = onenand_realize;
dc->reset = onenand_system_reset;
dc->props = onenand_properties;
}