* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
-#include <assert.h>
#include "cpu.h"
#include "exec-all.h"
#include "helper_regs.h"
+#include "qemu-common.h"
+#include "kvm.h"
//#define DEBUG_MMU
//#define DEBUG_BATS
+//#define DEBUG_SLB
//#define DEBUG_SOFTWARE_TLB
//#define DUMP_PAGE_TABLES
//#define DEBUG_EXCEPTIONS
//#define FLUSH_ALL_TLBS
+#ifdef DEBUG_MMU
+# define LOG_MMU(...) qemu_log(__VA_ARGS__)
+# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
+#else
+# define LOG_MMU(...) do { } while (0)
+# define LOG_MMU_STATE(...) do { } while (0)
+#endif
+
+
+#ifdef DEBUG_SOFTWARE_TLB
+# define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
+#else
+# define LOG_SWTLB(...) do { } while (0)
+#endif
+
+#ifdef DEBUG_BATS
+# define LOG_BATS(...) qemu_log(__VA_ARGS__)
+#else
+# define LOG_BATS(...) do { } while (0)
+#endif
+
+#ifdef DEBUG_SLB
+# define LOG_SLB(...) qemu_log(__VA_ARGS__)
+#else
+# define LOG_SLB(...) do { } while (0)
+#endif
+
+#ifdef DEBUG_EXCEPTIONS
+# define LOG_EXCP(...) qemu_log(__VA_ARGS__)
+#else
+# define LOG_EXCP(...) do { } while (0)
+#endif
+
+
/*****************************************************************************/
/* PowerPC MMU emulation */
#else
/* Common routines used by software and hardware TLBs emulation */
-static always_inline int pte_is_valid (target_ulong pte0)
+static inline int pte_is_valid(target_ulong pte0)
{
return pte0 & 0x80000000 ? 1 : 0;
}
-static always_inline void pte_invalidate (target_ulong *pte0)
+static inline void pte_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x80000000;
}
#if defined(TARGET_PPC64)
-static always_inline int pte64_is_valid (target_ulong pte0)
+static inline int pte64_is_valid(target_ulong pte0)
{
return pte0 & 0x0000000000000001ULL ? 1 : 0;
}
-static always_inline void pte64_invalidate (target_ulong *pte0)
+static inline void pte64_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x0000000000000001ULL;
}
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
#endif
-static always_inline int pp_check (int key, int pp, int nx)
+static inline int pp_check(int key, int pp, int nx)
{
int access;
return access;
}
-static always_inline int check_prot (int prot, int rw, int access_type)
+static inline int check_prot(int prot, int rw, int access_type)
{
int ret;
return ret;
}
-static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
target_ulong ptem, mmask;
int access, ret, pteh, ptev, pp;
ptem = pte0 & PTE64_PTEM_MASK;
mmask = PTE64_CHECK_MASK;
pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
- ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */
+ ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
} else
#endif
if (ctx->raddr != (target_phys_addr_t)-1ULL) {
/* all matches should have equal RPN, WIMG & PP */
if ((ctx->raddr & mmask) != (pte1 & mmask)) {
- if (loglevel != 0)
- fprintf(logfile, "Bad RPN/WIMG/PP\n");
+ qemu_log("Bad RPN/WIMG/PP\n");
return -3;
}
}
ret = check_prot(ctx->prot, rw, type);
if (ret == 0) {
/* Access granted */
-#if defined (DEBUG_MMU)
- if (loglevel != 0)
- fprintf(logfile, "PTE access granted !\n");
-#endif
+ LOG_MMU("PTE access granted !\n");
} else {
/* Access right violation */
-#if defined (DEBUG_MMU)
- if (loglevel != 0)
- fprintf(logfile, "PTE access rejected\n");
-#endif
+ LOG_MMU("PTE access rejected\n");
}
}
}
return ret;
}
-static always_inline int pte32_check (mmu_ctx_t *ctx,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
}
#if defined(TARGET_PPC64)
-static always_inline int pte64_check (mmu_ctx_t *ctx,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
}
#endif
-static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
- int ret, int rw)
+static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
+ int ret, int rw)
{
int store = 0;
}
/* Software driven TLB helpers */
-static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
- int way, int is_code)
+static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
+ int is_code)
{
int nr;
return nr;
}
-static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
+static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
{
ppc6xx_tlb_t *tlb;
int nr, max;
-#if defined (DEBUG_SOFTWARE_TLB) && 0
- if (loglevel != 0) {
- fprintf(logfile, "Invalidate all TLBs\n");
- }
-#endif
+ //LOG_SWTLB("Invalidate all TLBs\n");
/* Invalidate all defined software TLB */
max = env->nb_tlb;
if (env->id_tlbs == 1)
tlb_flush(env, 1);
}
-static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- int is_code,
- int match_epn)
+static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr,
+ int is_code, int match_epn)
{
#if !defined(FLUSH_ALL_TLBS)
ppc6xx_tlb_t *tlb;
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
tlb = &env->tlb[nr].tlb6;
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
- nr, env->nb_tlb, eaddr);
- }
-#endif
+ LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
+ env->nb_tlb, eaddr);
pte_invalidate(&tlb->pte0);
tlb_flush_page(env, tlb->EPN);
}
#endif
}
-static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- int is_code)
+static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr, int is_code)
{
__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
}
nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
tlb = &env->tlb[nr].tlb6;
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
- " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
- }
-#endif
+ LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
+ " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
/* Invalidate any pending reference in Qemu for this virtual address */
__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
tlb->pte0 = pte0;
env->last_way = way;
}
-static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw,
- int access_type)
+static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
{
ppc6xx_tlb_t *tlb;
int nr, best, way;
tlb = &env->tlb[nr].tlb6;
/* This test "emulates" the PTE index match for hardware TLBs */
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
- "] <> " ADDRX "\n",
- nr, env->nb_tlb,
- pte_is_valid(tlb->pte0) ? "valid" : "inval",
- tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
- }
-#endif
+ LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
+ "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
continue;
}
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
- " %c %c\n",
- nr, env->nb_tlb,
- pte_is_valid(tlb->pte0) ? "valid" : "inval",
- tlb->EPN, eaddr, tlb->pte1,
- rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
- }
-#endif
+ LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
+ TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, eaddr, tlb->pte1,
+ rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
case -3:
/* TLB inconsistency */
}
if (best != -1) {
done:
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
- ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
- }
-#endif
+ LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
+ ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
/* Update page flags */
pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
}
}
/* Perform BAT hit & translation */
-static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
- int *validp, int *protp,
- target_ulong *BATu, target_ulong *BATl)
+static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
+ int *protp, target_ulong *BATu,
+ target_ulong *BATl)
{
target_ulong bl;
int pp, valid, prot;
*protp = prot;
}
-static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
- int *validp, int *protp,
- target_ulong *BATu,
- target_ulong *BATl)
+static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
+ int *validp, int *protp,
+ target_ulong *BATu, target_ulong *BATl)
{
target_ulong bl;
int key, pp, valid, prot;
bl = (*BATl & 0x0000003F) << 17;
-#if defined (DEBUG_BATS)
- if (loglevel != 0) {
- fprintf(logfile, "b %02x ==> bl %08x msk %08x\n",
- *BATl & 0x0000003F, bl, ~bl);
- }
-#endif
+ LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
+ (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
prot = 0;
valid = (*BATl >> 6) & 1;
if (valid) {
*protp = prot;
}
-static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
- target_ulong virtual, int rw, int type)
+static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
+ int rw, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong base, BEPIl, BEPIu, bl;
int i, valid, prot;
int ret = -1;
-#if defined (DEBUG_BATS)
- if (loglevel != 0) {
- fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', virtual);
- }
-#endif
+ LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
+ type == ACCESS_CODE ? 'I' : 'D', virtual);
switch (type) {
case ACCESS_CODE:
BATlt = env->IBAT[1];
BATut = env->DBAT[0];
break;
}
-#if defined (DEBUG_BATS)
- if (loglevel != 0) {
- fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', virtual);
- }
-#endif
base = virtual & 0xFFFC0000;
for (i = 0; i < env->nb_BATs; i++) {
BATu = &BATut[i];
} else {
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
}
-#if defined (DEBUG_BATS)
- if (loglevel != 0) {
- fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
- " BATl 0x" ADDRX "\n",
- __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
- *BATu, *BATl);
- }
-#endif
+ LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
+ " BATl " TARGET_FMT_lx "\n", __func__,
+ type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
if ((virtual & 0xF0000000) == BEPIu &&
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
/* BAT matches */
/* Compute access rights */
ctx->prot = prot;
ret = check_prot(ctx->prot, rw, type);
-#if defined (DEBUG_BATS)
- if (ret == 0 && loglevel != 0) {
- fprintf(logfile, "BAT %d match: r 0x" PADDRX
- " prot=%c%c\n",
- i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
- ctx->prot & PAGE_WRITE ? 'W' : '-');
- }
-#endif
+ if (ret == 0)
+ LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
+ i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
+ ctx->prot & PAGE_WRITE ? 'W' : '-');
break;
}
}
}
if (ret < 0) {
-#if defined (DEBUG_BATS)
- if (loglevel != 0) {
- fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
+#if defined(DEBUG_BATS)
+ if (qemu_log_enabled()) {
+ LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
for (i = 0; i < 4; i++) {
BATu = &BATut[i];
BATl = &BATlt[i];
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
- fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
- " BATl 0x" ADDRX " \n\t"
- "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
- __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
- *BATu, *BATl, BEPIu, BEPIl, bl);
+ LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
+ " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "
+ TARGET_FMT_lx " " TARGET_FMT_lx "\n",
+ __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
+ *BATu, *BATl, BEPIu, BEPIl, bl);
}
}
#endif
}
-
/* No hit */
return ret;
}
/* PTE table lookup */
-static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
- int rw, int type)
+static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
+ int type, int target_page_bits)
{
target_ulong base, pte0, pte1;
int i, good = -1;
#if defined(TARGET_PPC64)
if (is_64b) {
pte0 = ldq_phys(base + (i * 16));
- pte1 = ldq_phys(base + (i * 16) + 8);
+ pte1 = ldq_phys(base + (i * 16) + 8);
+
+ /* We have a TLB that saves 4K pages, so let's
+ * split a huge page to 4k chunks */
+ if (target_page_bits != TARGET_PAGE_BITS)
+ pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1))
+ & TARGET_PAGE_MASK;
+
r = pte64_check(ctx, pte0, pte1, h, rw, type);
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
- " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
- base + (i * 16), pte0, pte1,
- (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
- ctx->ptem);
- }
-#endif
+ LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
+ TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
+ base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
+ (int)((pte0 >> 1) & 1), ctx->ptem);
} else
#endif
{
pte0 = ldl_phys(base + (i * 8));
pte1 = ldl_phys(base + (i * 8) + 4);
r = pte32_check(ctx, pte0, pte1, h, rw, type);
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
- " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
- base + (i * 8), pte0, pte1,
- (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
- ctx->ptem);
- }
-#endif
+ LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
+ TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
+ base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
+ (int)((pte0 >> 6) & 1), ctx->ptem);
}
switch (r) {
case -3:
}
if (good != -1) {
done:
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
- "ret=%d\n",
- ctx->raddr, ctx->prot, ret);
- }
-#endif
+ LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",
+ ctx->raddr, ctx->prot, ret);
/* Update page flags */
pte1 = ctx->raddr;
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
return ret;
}
-static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
+static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
+ int target_page_bits)
{
- return _find_pte(ctx, 0, h, rw, type);
+ return _find_pte(ctx, 0, h, rw, type, target_page_bits);
}
#if defined(TARGET_PPC64)
-static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
+static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
+ int target_page_bits)
{
- return _find_pte(ctx, 1, h, rw, type);
+ return _find_pte(ctx, 1, h, rw, type, target_page_bits);
}
#endif
-static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
- int h, int rw, int type)
+static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
+ int type, int target_page_bits)
{
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B)
- return find_pte64(ctx, h, rw, type);
+ if (env->mmu_model & POWERPC_MMU_64)
+ return find_pte64(ctx, h, rw, type, target_page_bits);
#endif
- return find_pte32(ctx, h, rw, type);
+ return find_pte32(ctx, h, rw, type, target_page_bits);
}
#if defined(TARGET_PPC64)
-static always_inline int slb_is_valid (uint64_t slb64)
+static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr)
{
- return slb64 & 0x0000000008000000ULL ? 1 : 0;
+ ppc_slb_t *retval = &env->slb[nr];
+
+#if 0 // XXX implement bridge mode?
+ if (env->spr[SPR_ASR] & 1) {
+ target_phys_addr_t sr_base;
+
+ sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;
+ sr_base += (12 * nr);
+
+ retval->tmp64 = ldq_phys(sr_base);
+ retval->tmp = ldl_phys(sr_base + 8);
+ }
+#endif
+
+ return retval;
+}
+
+static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
+{
+ ppc_slb_t *entry = &env->slb[nr];
+
+ if (slb == entry)
+ return;
+
+ entry->tmp64 = slb->tmp64;
+ entry->tmp = slb->tmp;
}
-static always_inline void slb_invalidate (uint64_t *slb64)
+static inline int slb_is_valid(ppc_slb_t *slb)
{
- *slb64 &= ~0x0000000008000000ULL;
+ return (int)(slb->tmp64 & 0x0000000008000000ULL);
}
-static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
- target_ulong *vsid,
- target_ulong *page_mask, int *attr)
+static inline void slb_invalidate(ppc_slb_t *slb)
+{
+ slb->tmp64 &= ~0x0000000008000000ULL;
+}
+
+static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
+ target_ulong *vsid, target_ulong *page_mask,
+ int *attr, int *target_page_bits)
{
- target_phys_addr_t sr_base;
target_ulong mask;
- uint64_t tmp64;
- uint32_t tmp;
int n, ret;
ret = -5;
- sr_base = env->spr[SPR_ASR];
-#if defined(DEBUG_SLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
- __func__, eaddr, sr_base);
- }
-#endif
+ LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
mask = 0x0000000000000000ULL; /* Avoid gcc warning */
for (n = 0; n < env->slb_nr; n++) {
- tmp64 = ldq_phys(sr_base);
- tmp = ldl_phys(sr_base + 8);
-#if defined(DEBUG_SLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"
- PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
- }
-#endif
- if (slb_is_valid(tmp64)) {
+ ppc_slb_t *slb = slb_get_entry(env, n);
+
+ LOG_SLB("%s: seg %d %016" PRIx64 " %08"
+ PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);
+ if (slb_is_valid(slb)) {
/* SLB entry is valid */
- switch (tmp64 & 0x0000000006000000ULL) {
- case 0x0000000000000000ULL:
- /* 256 MB segment */
- mask = 0xFFFFFFFFF0000000ULL;
- break;
- case 0x0000000002000000ULL:
- /* 1 TB segment */
+ if (slb->tmp & 0x8) {
+ /* 1 TB Segment */
mask = 0xFFFF000000000000ULL;
- break;
- case 0x0000000004000000ULL:
- case 0x0000000006000000ULL:
- /* Reserved => segment is invalid */
- continue;
+ if (target_page_bits)
+ *target_page_bits = 24; // XXX 16M pages?
+ } else {
+ /* 256MB Segment */
+ mask = 0xFFFFFFFFF0000000ULL;
+ if (target_page_bits)
+ *target_page_bits = TARGET_PAGE_BITS;
}
- if ((eaddr & mask) == (tmp64 & mask)) {
+ if ((eaddr & mask) == (slb->tmp64 & mask)) {
/* SLB match */
- *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
+ *vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
*page_mask = ~mask;
- *attr = tmp & 0xFF;
+ *attr = slb->tmp & 0xFF;
ret = n;
break;
}
}
- sr_base += 12;
}
return ret;
void ppc_slb_invalidate_all (CPUPPCState *env)
{
- target_phys_addr_t sr_base;
- uint64_t tmp64;
int n, do_invalidate;
do_invalidate = 0;
- sr_base = env->spr[SPR_ASR];
/* XXX: Warning: slbia never invalidates the first segment */
for (n = 1; n < env->slb_nr; n++) {
- tmp64 = ldq_phys(sr_base);
- if (slb_is_valid(tmp64)) {
- slb_invalidate(&tmp64);
- stq_phys(sr_base, tmp64);
+ ppc_slb_t *slb = slb_get_entry(env, n);
+
+ if (slb_is_valid(slb)) {
+ slb_invalidate(slb);
+ slb_set_entry(env, n, slb);
/* XXX: given the fact that segment size is 256 MB or 1TB,
* and we still don't have a tlb_flush_mask(env, n, mask)
* in Qemu, we just invalidate all TLBs
*/
do_invalidate = 1;
}
- sr_base += 12;
}
if (do_invalidate)
tlb_flush(env, 1);
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
{
- target_phys_addr_t sr_base;
target_ulong vsid, page_mask;
- uint64_t tmp64;
int attr;
int n;
- n = slb_lookup(env, T0, &vsid, &page_mask, &attr);
+ n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
if (n >= 0) {
- sr_base = env->spr[SPR_ASR];
- sr_base += 12 * n;
- tmp64 = ldq_phys(sr_base);
- if (slb_is_valid(tmp64)) {
- slb_invalidate(&tmp64);
- stq_phys(sr_base, tmp64);
+ ppc_slb_t *slb = slb_get_entry(env, n);
+
+ if (slb_is_valid(slb)) {
+ slb_invalidate(slb);
+ slb_set_entry(env, n, slb);
/* XXX: given the fact that segment size is 256 MB or 1TB,
* and we still don't have a tlb_flush_mask(env, n, mask)
* in Qemu, we just invalidate all TLBs
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
{
- target_phys_addr_t sr_base;
target_ulong rt;
- uint64_t tmp64;
- uint32_t tmp;
-
- sr_base = env->spr[SPR_ASR];
- sr_base += 12 * slb_nr;
- tmp64 = ldq_phys(sr_base);
- tmp = ldl_phys(sr_base + 8);
- if (tmp64 & 0x0000000008000000ULL) {
+ ppc_slb_t *slb = slb_get_entry(env, slb_nr);
+
+ if (slb_is_valid(slb)) {
/* SLB entry is valid */
/* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
- rt = tmp >> 8; /* 65:88 => 40:63 */
- rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
+ rt = slb->tmp >> 8; /* 65:88 => 40:63 */
+ rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
/* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
- rt |= ((tmp >> 4) & 0xF) << 27;
+ rt |= ((slb->tmp >> 4) & 0xF) << 27;
} else {
rt = 0;
}
-#if defined(DEBUG_SLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
- ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
- }
-#endif
+ LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
+ TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
return rt;
}
-void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
-{
- target_phys_addr_t sr_base;
- uint64_t tmp64;
- uint32_t tmp;
-
- sr_base = env->spr[SPR_ASR];
- sr_base += 12 * slb_nr;
- /* Copy Rs bits 37:63 to SLB 62:88 */
- tmp = rs << 8;
- tmp64 = (rs >> 24) & 0x7;
- /* Copy Rs bits 33:36 to SLB 89:92 */
- tmp |= ((rs >> 27) & 0xF) << 4;
- /* Set the valid bit */
- tmp64 |= 1 << 27;
- /* Set ESID */
- tmp64 |= (uint32_t)slb_nr << 28;
-#if defined(DEBUG_SLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08"
- PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);
- }
-#endif
- /* Write SLB entry to memory */
- stq_phys(sr_base, tmp64);
- stl_phys(sr_base + 8, tmp);
+void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
+{
+ ppc_slb_t *slb;
+
+ uint64_t vsid;
+ uint64_t esid;
+ int flags, valid, slb_nr;
+
+ vsid = rs >> 12;
+ flags = ((rs >> 8) & 0xf);
+
+ esid = rb >> 28;
+ valid = (rb & (1 << 27));
+ slb_nr = rb & 0xfff;
+
+ slb = slb_get_entry(env, slb_nr);
+ slb->tmp64 = (esid << 28) | valid | (vsid >> 24);
+ slb->tmp = (vsid << 8) | (flags << 3);
+
+ LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
+ " %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64,
+ slb->tmp);
+
+ slb_set_entry(env, slb_nr, slb);
}
#endif /* defined(TARGET_PPC64) */
/* Perform segment based translation */
-static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
- int sdr_sh,
- target_phys_addr_t hash,
- target_phys_addr_t mask)
+static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
+ int sdr_sh,
+ target_phys_addr_t hash,
+ target_phys_addr_t mask)
{
return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
}
-static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type)
+static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
#if defined(TARGET_PPC64)
int attr;
#endif
- int ds, vsid_sh, sdr_sh, pr;
+ int ds, vsid_sh, sdr_sh, pr, target_page_bits;
int ret, ret2;
pr = msr_pr;
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B) {
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "Check SLBs\n");
- }
-#endif
- ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
+ if (env->mmu_model & POWERPC_MMU_64) {
+ LOG_MMU("Check SLBs\n");
+ ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr,
+ &target_page_bits);
if (ret < 0)
return ret;
ctx->key = ((attr & 0x40) && (pr != 0)) ||
((attr & 0x80) && (pr == 0)) ? 1 : 0;
ds = 0;
- ctx->nx = attr & 0x20 ? 1 : 0;
+ ctx->nx = attr & 0x10 ? 1 : 0;
+ ctx->eaddr = eaddr;
vsid_mask = 0x00003FFFFFFFFF80ULL;
vsid_sh = 7;
sdr_sh = 18;
vsid_sh = 6;
sdr_sh = 16;
sdr_mask = 0xFFC0;
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
- " nip=0x" ADDRX " lr=0x" ADDRX
- " ir=%d dr=%d pr=%d %d t=%d\n",
- eaddr, (int)(eaddr >> 28), sr, env->nip,
- env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
- rw, type);
- }
-#endif
- }
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
- ctx->key, ds, ctx->nx, vsid);
- }
-#endif
+ target_page_bits = TARGET_PAGE_BITS;
+ LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
+ TARGET_FMT_lx " lr=" TARGET_FMT_lx
+ " ir=%d dr=%d pr=%d %d t=%d\n",
+ eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
+ (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
+ }
+ LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
+ ctx->key, ds, ctx->nx, vsid);
ret = -1;
if (!ds) {
/* Check if instruction fetch is allowed, if needed */
/* Page address translation */
/* Primary table address */
sdr = env->sdr1;
- pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
+ pgidx = (eaddr & page_mask) >> target_page_bits;
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B) {
+ if (env->mmu_model & POWERPC_MMU_64) {
htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
/* XXX: this is false for 1 TB segments */
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
}
mask = (htab_mask << sdr_sh) | sdr_mask;
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
- PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask,
- page_mask);
- }
-#endif
+ LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
+ " mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
+ sdr, sdr_sh, hash, mask, page_mask);
ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
/* Secondary table address */
hash = (~hash) & vsid_mask;
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
- PADDRX "\n", sdr, sdr_sh, hash, mask);
- }
-#endif
+ LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
+ " mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask);
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
#if defined(TARGET_PPC64)
- if (env->mmu_model == POWERPC_MMU_64B) {
+ if (env->mmu_model & POWERPC_MMU_64) {
/* Only 5 bits of the page index are used in the AVPN */
- ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
+ if (target_page_bits > 23) {
+ ctx->ptem = (vsid << 12) |
+ ((pgidx << (target_page_bits - 16)) & 0xF80);
+ } else {
+ ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
+ }
} else
#endif
{
/* Software TLB search */
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
} else {
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
- "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
- sdr, (uint32_t)vsid, (uint32_t)pgidx,
- (uint32_t)hash, ctx->pg_addr[0]);
- }
-#endif
+ LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
+ "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
+ " pg_addr=" TARGET_FMT_plx "\n",
+ sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
/* Primary table lookup */
- ret = find_pte(env, ctx, 0, rw, type);
+ ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
if (ret < 0) {
/* Secondary table lookup */
-#if defined (DEBUG_MMU)
- if (eaddr != 0xEFFFFFFF && loglevel != 0) {
- fprintf(logfile,
- "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
- "hash=0x%05x pg_addr=0x" PADDRX "\n",
- sdr, (uint32_t)vsid, (uint32_t)pgidx,
- (uint32_t)hash, ctx->pg_addr[1]);
- }
-#endif
- ret2 = find_pte(env, ctx, 1, rw, type);
+ if (eaddr != 0xEFFFFFFF)
+ LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
+ "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
+ " pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
+ pgidx, hash, ctx->pg_addr[1]);
+ ret2 = find_pte(env, ctx, 1, rw, type,
+ target_page_bits);
if (ret2 != -1)
ret = ret2;
}
}
#if defined (DUMP_PAGE_TABLES)
- if (loglevel != 0) {
+ if (qemu_log_enabled()) {
target_phys_addr_t curaddr;
uint32_t a0, a1, a2, a3;
- fprintf(logfile,
- "Page table: " PADDRX " len " PADDRX "\n",
- sdr, mask + 0x80);
+ qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
+ "\n", sdr, mask + 0x80);
for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
curaddr += 16) {
a0 = ldl_phys(curaddr);
a2 = ldl_phys(curaddr + 8);
a3 = ldl_phys(curaddr + 12);
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
- fprintf(logfile,
- PADDRX ": %08x %08x %08x %08x\n",
- curaddr, a0, a1, a2, a3);
+ qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
+ curaddr, a0, a1, a2, a3);
}
}
}
#endif
} else {
-#if defined (DEBUG_MMU)
- if (loglevel != 0)
- fprintf(logfile, "No access allowed\n");
-#endif
+ LOG_MMU("No access allowed\n");
ret = -3;
}
} else {
-#if defined (DEBUG_MMU)
- if (loglevel != 0)
- fprintf(logfile, "direct store...\n");
-#endif
+ LOG_MMU("direct store...\n");
/* Direct-store segment : absolutely *BUGGY* for now */
switch (type) {
case ACCESS_INT:
/* eciwx or ecowx */
return -4;
default:
- if (logfile) {
- fprintf(logfile, "ERROR: instruction should not need "
+ qemu_log("ERROR: instruction should not need "
"address translation\n");
- }
return -4;
}
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
}
/* Generic TLB check function for embedded PowerPC implementations */
-static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddrp,
- target_ulong address,
- uint32_t pid, int ext, int i)
+static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
+ target_phys_addr_t *raddrp,
+ target_ulong address, uint32_t pid, int ext,
+ int i)
{
target_ulong mask;
/* Check valid flag */
if (!(tlb->prot & PAGE_VALID)) {
- if (loglevel != 0)
- fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
+ qemu_log("%s: TLB %d not valid\n", __func__, i);
return -1;
}
mask = ~(tlb->size - 1);
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
- ADDRX " " ADDRX " %d\n",
- __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
- }
-#endif
+ LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
+ " " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN,
+ mask, (uint32_t)tlb->PID);
/* Check PID */
if (tlb->PID != 0 && tlb->PID != pid)
return -1;
}
/* Helpers specific to PowerPC 40x implementations */
-static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
+static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
{
ppcemb_tlb_t *tlb;
int i;
tlb_flush(env, 1);
}
-static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- uint32_t pid)
+static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr, uint32_t pid)
{
#if !defined(FLUSH_ALL_TLBS)
ppcemb_tlb_t *tlb;
#endif
}
-int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
+static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
target_ulong address, int rw, int access_type)
{
ppcemb_tlb_t *tlb;
continue;
zsel = (tlb->attr >> 4) & 0xF;
zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
+ LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
__func__, i, zsel, zpr, rw, tlb->attr);
- }
-#endif
/* Check execute enable bit */
switch (zpr) {
case 0x2:
}
if (ret >= 0) {
ctx->raddr = raddr;
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: access granted " ADDRX " => " REGX
- " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
- ret);
- }
-#endif
+ LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
+ " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
+ ret);
return 0;
}
}
-#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- fprintf(logfile, "%s: access refused " ADDRX " => " REGX
- " %d %d\n", __func__, address, raddr, ctx->prot,
- ret);
- }
-#endif
+ LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
+ " %d %d\n", __func__, address, raddr, ctx->prot, ret);
return ret;
}
env->spr[SPR_405_SLER] = val;
}
-int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
- target_ulong address, int rw,
- int access_type)
+static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong address, int rw,
+ int access_type)
{
ppcemb_tlb_t *tlb;
target_phys_addr_t raddr;
return ret;
}
-static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw)
+static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw)
{
int in_plb, ret;
ctx->prot |= PAGE_WRITE;
break;
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
/* Real address are 60 bits long */
ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
int ret;
#if 0
- if (loglevel != 0) {
- fprintf(logfile, "%s\n", __func__);
- }
+ qemu_log("%s\n", __func__);
#endif
if ((access_type == ACCESS_CODE && msr_ir == 0) ||
(access_type != ACCESS_CODE && msr_dr == 0)) {
case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_64B:
-#endif
/* Try to find a BAT */
if (env->nb_BATs != 0)
ret = get_bat(env, ctx, eaddr, rw, access_type);
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
+ case POWERPC_MMU_64B:
+#endif
if (ret < 0) {
/* We didn't match any BAT entry or don't have BATs */
ret = get_segment(env, ctx, eaddr, rw, access_type);
}
}
#if 0
- if (loglevel != 0) {
- fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
- __func__, eaddr, ret, ctx->raddr);
- }
+ qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
+ __func__, eaddr, ret, ctx->raddr);
#endif
return ret;
access_type = ACCESS_CODE;
} else {
/* data access */
- /* XXX: put correct access by using cpu_restore_state()
- correctly */
- access_type = ACCESS_INT;
- // access_type = env->access_type;
+ access_type = env->access_type;
}
ret = get_physical_address(env, &ctx, address, rw, access_type);
if (ret == 0) {
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
mmu_idx, is_softmmu);
} else if (ret < 0) {
-#if defined (DEBUG_MMU)
- if (loglevel != 0)
- cpu_dump_state(env, logfile, fprintf, 0);
-#endif
+ LOG_MMU_STATE(env);
if (access_type == ACCESS_CODE) {
switch (ret) {
case -1:
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif
env->exception_index = POWERPC_EXCP_ISI;
#if defined(TARGET_PPC64)
case -5:
/* No match in segment table */
- env->exception_index = POWERPC_EXCP_ISEG;
- env->error_code = 0;
+ if (env->mmu_model == POWERPC_MMU_620) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ /* XXX: this might be incorrect */
+ env->error_code = 0x40000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_ISEG;
+ env->error_code = 0;
+ }
break;
#endif
}
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif
env->exception_index = POWERPC_EXCP_DSI;
#if defined(TARGET_PPC64)
case -5:
/* No match in segment table */
- env->exception_index = POWERPC_EXCP_DSEG;
- env->error_code = 0;
- env->spr[SPR_DAR] = address;
+ if (env->mmu_model == POWERPC_MMU_620) {
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = address;
+ /* XXX: this might be incorrect */
+ if (rw == 1)
+ env->spr[SPR_DSISR] = 0x42000000;
+ else
+ env->spr[SPR_DSISR] = 0x40000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSEG;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = address;
+ }
break;
#endif
}
/*****************************************************************************/
/* BATs management */
#if !defined(FLUSH_ALL_TLBS)
-static always_inline void do_invalidate_BAT (CPUPPCState *env,
- target_ulong BATu,
- target_ulong mask)
+static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
+ target_ulong mask)
{
target_ulong base, end, page;
base = BATu & ~0x0001FFFF;
end = base + mask + 0x00020000;
-#if defined (DEBUG_BATS)
- if (loglevel != 0) {
- fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
- base, end, mask);
- }
-#endif
+ LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
+ TARGET_FMT_lx ")\n", base, end, mask);
for (page = base; page != end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
-#if defined (DEBUG_BATS)
- if (loglevel != 0)
- fprintf(logfile, "Flush done\n");
-#endif
+ LOG_BATS("Flush done\n");
}
#endif
-static always_inline void dump_store_bat (CPUPPCState *env, char ID,
- int ul, int nr, target_ulong value)
-{
-#if defined (DEBUG_BATS)
- if (loglevel != 0) {
- fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
- ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
- }
-#endif
-}
-
-target_ulong do_load_ibatu (CPUPPCState *env, int nr)
-{
- return env->IBAT[0][nr];
-}
-
-target_ulong do_load_ibatl (CPUPPCState *env, int nr)
+static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
+ target_ulong value)
{
- return env->IBAT[1][nr];
+ LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
+ nr, ul == 0 ? 'u' : 'l', value, env->nip);
}
-void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
+void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
{
target_ulong mask;
}
}
-void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
+void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
{
dump_store_bat(env, 'I', 1, nr, value);
env->IBAT[1][nr] = value;
}
-target_ulong do_load_dbatu (CPUPPCState *env, int nr)
-{
- return env->DBAT[0][nr];
-}
-
-target_ulong do_load_dbatl (CPUPPCState *env, int nr)
-{
- return env->DBAT[1][nr];
-}
-
-void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
+void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
{
target_ulong mask;
}
}
-void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
+void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
{
dump_store_bat(env, 'D', 1, nr, value);
env->DBAT[1][nr] = value;
}
-void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
+void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
{
target_ulong mask;
int do_inval;
}
}
-void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
+void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
{
target_ulong mask;
int do_inval;
break;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
- cpu_abort(env, "BookE MMU model is not implemented\n");
+ if (!kvm_enabled())
+ cpu_abort(env, "BookE MMU model is not implemented\n");
break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif /* defined(TARGET_PPC64) */
tlb_flush(env, 1);
tlb_flush_page(env, addr | (0xF << 28));
break;
#if defined(TARGET_PPC64)
+ case POWERPC_MMU_620:
case POWERPC_MMU_64B:
/* tlbie invalidate TLBs for all segments */
/* XXX: given the fact that there are too many segments to invalidate,
/*****************************************************************************/
/* Special registers manipulation */
#if defined(TARGET_PPC64)
-target_ulong ppc_load_asr (CPUPPCState *env)
-{
- return env->asr;
-}
-
void ppc_store_asr (CPUPPCState *env, target_ulong value)
{
if (env->asr != value) {
}
#endif
-target_ulong do_load_sdr1 (CPUPPCState *env)
+void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
{
- return env->sdr1;
-}
-
-void do_store_sdr1 (CPUPPCState *env, target_ulong value)
-{
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
- }
-#endif
+ LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
if (env->sdr1 != value) {
/* XXX: for PowerPC 64, should check that the HTABSIZE value
* is <= 28
}
}
-#if 0 // Unused
-target_ulong do_load_sr (CPUPPCState *env, int srnum)
+#if defined(TARGET_PPC64)
+target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
{
- return env->sr[srnum];
+ // XXX
+ return 0;
}
#endif
-void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
+void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
{
-#if defined (DEBUG_MMU)
- if (loglevel != 0) {
- fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
- __func__, srnum, value, env->sr[srnum]);
- }
+ LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
+ srnum, value, env->sr[srnum]);
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64) {
+ uint64_t rb = 0, rs = 0;
+
+ /* ESID = srnum */
+ rb |= ((uint32_t)srnum & 0xf) << 28;
+ /* Set the valid bit */
+ rb |= 1 << 27;
+ /* Index = ESID */
+ rb |= (uint32_t)srnum;
+
+ /* VSID = VSID */
+ rs |= (value & 0xfffffff) << 12;
+ /* flags = flags */
+ rs |= ((value >> 27) & 0xf) << 9;
+
+ ppc_store_slb(env, rb, rs);
+ } else
#endif
if (env->sr[srnum] != value) {
env->sr[srnum] = value;
+/* Invalidating 256MB of virtual memory in 4kB pages is way longer than
+ flusing the whole TLB. */
#if !defined(FLUSH_ALL_TLBS) && 0
{
target_ulong page, end;
}
#endif /* !defined (CONFIG_USER_ONLY) */
-target_ulong ppc_load_xer (CPUPPCState *env)
-{
- return hreg_load_xer(env);
-}
-
-void ppc_store_xer (CPUPPCState *env, target_ulong value)
-{
- hreg_store_xer(env, value);
-}
-
/* GDBstub can read and write MSR... */
void ppc_store_msr (CPUPPCState *env, target_ulong value)
{
env->error_code = 0;
}
#else /* defined (CONFIG_USER_ONLY) */
-static always_inline void dump_syscall (CPUState *env)
+static inline void dump_syscall(CPUState *env)
{
- fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
- " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
- env->gpr[0], env->gpr[3], env->gpr[4],
- env->gpr[5], env->gpr[6], env->nip);
+ qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
+ " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
+ " nip=" TARGET_FMT_lx "\n",
+ ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
+ ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
+ ppc_dump_gpr(env, 6), env->nip);
}
/* Note that this function should be greatly optimized
* when called with a constant excp, from ppc_hw_interrupt
*/
-static always_inline void powerpc_excp (CPUState *env,
- int excp_model, int excp)
+static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
lpes1 = 1;
}
- if (loglevel & CPU_LOG_INT) {
- fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
- env->nip, excp, env->error_code);
- }
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %08x (%02x)\n", env->nip, excp, env->error_code);
msr = env->msr;
new_msr = msr;
srr0 = SPR_SRR0;
/* Machine check exception is not enabled.
* Enter checkstop state.
*/
- if (loglevel != 0) {
- fprintf(logfile, "Machine check while not allowed. "
+ if (qemu_log_enabled()) {
+ qemu_log("Machine check while not allowed. "
"Entering checkstop state\n");
} else {
fprintf(stderr, "Machine check while not allowed. "
}
goto store_next;
case POWERPC_EXCP_DSI: /* Data storage exception */
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0) {
- fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
- "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
- }
-#endif
+ LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
+ "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0) {
- fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
- "\n", msr, env->nip);
- }
-#endif
+ LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
+ "\n", msr, env->nip);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0) {
- fprintf(logfile, "Ignore floating point exception\n");
- }
-#endif
+ LOG_EXCP("Ignore floating point exception\n");
env->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
return;
msr |= 0x00010000;
break;
case POWERPC_EXCP_INVAL:
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0) {
- fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
- env->nip);
- }
-#endif
+ LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
return;
}
}
- if (loglevel & CPU_LOG_INT) {
- dump_syscall(env);
- }
+ dump_syscall(env);
new_msr &= ~((target_ulong)1 << MSR_RI);
lev = env->error_code;
if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
goto store_next;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
/* FIT on 4xx */
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0)
- fprintf(logfile, "FIT exception\n");
-#endif
+ LOG_EXCP("FIT exception\n");
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
goto store_next;
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0)
- fprintf(logfile, "WDT exception\n");
-#endif
+ LOG_EXCP("WDT exception\n");
switch (excp_model) {
case POWERPC_EXCP_BOOKE:
srr0 = SPR_BOOKE_CSRR0;
new_msr |= (target_ulong)MSR_HVB;
goto store_current;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0)
- fprintf(logfile, "PIT exception\n");
-#endif
+ LOG_EXCP("PIT exception\n");
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
goto store_next;
case POWERPC_EXCP_IO: /* IO error exception */
case POWERPC_EXCP_7x5:
tlb_miss:
#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- const unsigned char *es;
+ if (qemu_log_enabled()) {
+ const char *es;
target_ulong *miss, *cmp;
int en;
if (excp == POWERPC_EXCP_IFTLB) {
miss = &env->spr[SPR_DMISS];
cmp = &env->spr[SPR_DCMP];
}
- fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
- " H1 " ADDRX " H2 " ADDRX " %08x\n",
- es, en, *miss, en, *cmp,
- env->spr[SPR_HASH1], env->spr[SPR_HASH2],
- env->error_code);
+ qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
+ TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
+ TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
+ env->spr[SPR_HASH1], env->spr[SPR_HASH2],
+ env->error_code);
}
#endif
msr |= env->crf[0] << 28;
case POWERPC_EXCP_74xx:
tlb_miss_74xx:
#if defined (DEBUG_SOFTWARE_TLB)
- if (loglevel != 0) {
- const unsigned char *es;
+ if (qemu_log_enabled()) {
+ const char *es;
target_ulong *miss, *cmp;
int en;
if (excp == POWERPC_EXCP_IFTLB) {
miss = &env->spr[SPR_TLBMISS];
cmp = &env->spr[SPR_PTEHI];
}
- fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
- " %08x\n",
- es, en, *miss, en, *cmp, env->error_code);
+ qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
+ TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
+ env->error_code);
}
#endif
msr |= env->error_code; /* key bit */
new_msr |= (target_ulong)1 << MSR_CM;
}
} else {
- if (!msr_isf) {
+ if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
new_msr &= ~((target_ulong)1 << MSR_SF);
vector = (uint32_t)vector;
} else {
int hdice;
#if 0
- if (loglevel & CPU_LOG_INT) {
- fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
+ qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
__func__, env, env->pending_interrupts,
env->interrupt_request, (int)msr_me, (int)msr_ee);
- }
#endif
/* External reset */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
}
#endif /* !CONFIG_USER_ONLY */
-void cpu_dump_EA (target_ulong EA)
-{
- FILE *f;
-
- if (logfile) {
- f = logfile;
- } else {
- f = stdout;
- return;
- }
- fprintf(f, "Memory access at address " ADDRX "\n", EA);
-}
-
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
{
- FILE *f;
-
- if (logfile) {
- f = logfile;
- } else {
- f = stdout;
- return;
- }
- fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
- RA, msr);
+ qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
+ TARGET_FMT_lx "\n", RA, msr);
}
-void cpu_ppc_reset (void *opaque)
+void cpu_reset(CPUPPCState *env)
{
- CPUPPCState *env;
target_ulong msr;
- env = opaque;
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
msr = (target_ulong)0;
if (0) {
/* XXX: find a suitable condition to enable the hypervisor mode */
#endif
#if defined(CONFIG_USER_ONLY)
msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
+ msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
+ msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
msr |= (target_ulong)1 << MSR_PR;
#else
+ env->excp_prefix = env->hreset_excp_prefix;
env->nip = env->hreset_vector | env->excp_prefix;
if (env->mmu_model != POWERPC_MMU_REAL)
ppc_tlb_invalidate_all(env);
#endif
- env->msr = msr;
+ env->msr = msr & env->msr_mask;
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64)
+ env->msr |= (1ULL << MSR_SF);
+#endif
hreg_compute_hflags(env);
- env->reserve = (target_ulong)-1ULL;
+ env->reserve_addr = (target_ulong)-1ULL;
/* Be sure no exception or interrupt is pending */
env->pending_interrupts = 0;
env->exception_index = POWERPC_EXCP_NONE;
return NULL;
env = qemu_mallocz(sizeof(CPUPPCState));
- if (!env)
- return NULL;
cpu_exec_init(env);
+ ppc_translate_init();
+ env->cpu_model_str = cpu_model;
cpu_ppc_register_internal(env, def);
- cpu_ppc_reset(env);
+
+ qemu_init_vcpu(env);
+
return env;
}
projects / qemu.git / blobdiff