* for more details.
*/
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+#include "cpu.h"
#include "hw/sysbus.h"
-#include "hw/devices.h"
#include "hw/arm/allwinner-a10.h"
+#include "hw/misc/unimp.h"
static void aw_a10_init(Object *obj)
{
AwA10State *s = AW_A10(obj);
- object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a8-" TYPE_ARM_CPU);
- object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
+ object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
+ "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL);
- object_initialize(&s->intc, sizeof(s->intc), TYPE_AW_A10_PIC);
- qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
+ sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
+ TYPE_AW_A10_PIC);
- object_initialize(&s->timer, sizeof(s->timer), TYPE_AW_A10_PIT);
- qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
+ TYPE_AW_A10_PIT);
- object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
- qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
- /* FIXME use qdev NIC properties instead of nd_table[] */
- if (nd_table[0].used) {
- qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
- qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
- }
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC);
- object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
- qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
+ sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
+ TYPE_ALLWINNER_AHCI);
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
+ memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
+ &error_fatal);
+ memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
+ create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
+
+ /* FIXME use qdev NIC properties instead of nd_table[] */
+ if (nd_table[0].used) {
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
+ }
object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
- /* FIXME use a qdev chardev prop instead of serial_hds[] */
+ /* FIXME use a qdev chardev prop instead of serial_hd() */
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
- 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
}
static void aw_a10_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = aw_a10_realize;
-
- /*
- * Reason: creates an ARM CPU, thus use after free(), see
- * arm_cpu_class_init()
- */
- dc->cannot_destroy_with_object_finalize_yet = true;
+ /* Reason: Uses serial_hds and nd_table in realize function */
+ dc->user_creatable = false;
}
static const TypeInfo aw_a10_type_info = {