cpu_outb(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
cpu_outl(addr & IOPORTS_MASK, val);
}
static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
{
- uint32_t val;
-
- val = cpu_inb(addr & IOPORTS_MASK);
- return val;
+ return cpu_inb(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
{
- uint32_t val;
-
- val = cpu_inw(addr & IOPORTS_MASK);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
- return val;
+ return cpu_inw(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
{
- uint32_t val;
-
- val = cpu_inl(addr & IOPORTS_MASK);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- return val;
+ return cpu_inl(addr & IOPORTS_MASK);
}
static CPUWriteMemoryFunc * const isa_mmio_write[] = {
&isa_mmio_readl,
};
-static int isa_mmio_iomemtype = 0;
-
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
{
- if (!isa_mmio_iomemtype) {
- isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
- isa_mmio_write, NULL);
- }
+ int isa_mmio_iomemtype;
+
+ isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
+ isa_mmio_write,
+ NULL,
+ DEVICE_LITTLE_ENDIAN);
cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
}