#define MAX_PACKET_LENGTH 4096
+#include "cpu.h"
#include "qemu_socket.h"
#include "kvm.h"
+#ifndef TARGET_CPU_MEMORY_RW_DEBUG
+static inline int target_memory_rw_debug(CPUState *env, target_ulong addr,
+ uint8_t *buf, int len, int is_write)
+{
+ return cpu_memory_rw_debug(env, addr, buf, len, is_write);
+}
+#else
+/* target_memory_rw_debug() defined in cpu.h */
+#endif
enum {
GDB_SIGNAL_0 = 0,
GDB_SIGNAL_INT = 2,
+ GDB_SIGNAL_QUIT = 3,
GDB_SIGNAL_TRAP = 5,
+ GDB_SIGNAL_ABRT = 6,
+ GDB_SIGNAL_ALRM = 14,
+ GDB_SIGNAL_IO = 23,
+ GDB_SIGNAL_XCPU = 24,
GDB_SIGNAL_UNKNOWN = 143
};
int ret;
for(;;) {
- ret = recv(s->fd, &ch, 1, 0);
+ ret = qemu_recv(s->fd, &ch, 1, 0);
if (ret < 0) {
if (errno == ECONNRESET)
s->fd = -1;
}
}
#else
- qemu_chr_write(s->chr, buf, len);
+ qemu_chr_fe_write(s->chr, buf, len);
#endif
}
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
switch (n) {
case 64: GET_REGA(env->y);
- case 65: GET_REGA(GET_PSR(env));
+ case 65: GET_REGA(cpu_get_psr(env));
case 66: GET_REGA(env->wim);
case 67: GET_REGA(env->tbr);
case 68: GET_REGA(env->pc);
switch (n) {
case 80: GET_REGL(env->pc);
case 81: GET_REGL(env->npc);
- case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
- ((env->asi & 0xff) << 24) |
- ((env->pstate & 0xfff) << 8) |
- GET_CWP64(env));
+ case 82: GET_REGL((cpu_get_ccr(env) << 32) |
+ ((env->asi & 0xff) << 24) |
+ ((env->pstate & 0xfff) << 8) |
+ cpu_get_cwp64(env));
case 83: GET_REGL(env->fsr);
case 84: GET_REGL(env->fprs);
case 85: GET_REGL(env->y);
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
switch (n) {
case 64: env->y = tmp; break;
- case 65: PUT_PSR(env, tmp); break;
+ case 65: cpu_put_psr(env, tmp); break;
case 66: env->wim = tmp; break;
case 67: env->tbr = tmp; break;
case 68: env->pc = tmp; break;
case 80: env->pc = tmp; break;
case 81: env->npc = tmp; break;
case 82:
- PUT_CCR(env, tmp >> 32);
+ cpu_put_ccr(env, tmp >> 32);
env->asi = (tmp >> 24) & 0xff;
env->pstate = (tmp >> 8) & 0xfff;
- PUT_CWP64(env, tmp & 0xff);
+ cpu_put_cwp64(env, tmp & 0xff);
break;
case 83: env->fsr = tmp; break;
case 84: env->fprs = tmp; break;
if (n < 8) {
/* D0-D7 */
env->dregs[n] = tmp;
- } else if (n < 8) {
+ } else if (n < 16) {
/* A0-A7 */
env->aregs[n - 8] = tmp;
} else {
case 34: GET_REGL(env->active_tc.HI[0]);
case 35: GET_REGL(env->CP0_BadVAddr);
case 36: GET_REGL((int32_t)env->CP0_Cause);
- case 37: GET_REGL(env->active_tc.PC);
+ case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
case 72: GET_REGL(0); /* fp */
case 89: GET_REGL((int32_t)env->CP0_PRid);
}
env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
/* set rounding mode */
RESTORE_ROUNDING_MODE;
-#ifndef CONFIG_SOFTFLOAT
- /* no floating point exception for native float */
- SET_FP_ENABLE(env->active_fpu.fcr31, 0);
-#endif
break;
case 71: env->active_fpu.fcr0 = tmp; break;
}
case 34: env->active_tc.HI[0] = tmp; break;
case 35: env->CP0_BadVAddr = tmp; break;
case 36: env->CP0_Cause = tmp; break;
- case 37: env->active_tc.PC = tmp; break;
+ case 37:
+ env->active_tc.PC = tmp & ~(target_ulong)1;
+ if (tmp & 1) {
+ env->hflags |= MIPS_HFLAG_M16;
+ } else {
+ env->hflags &= ~(MIPS_HFLAG_M16);
+ }
+ break;
case 72: /* fp, ignored */ break;
default:
if (n > 89)
GET_REGL(env->gregs[n]);
}
} else if (n < 16) {
- GET_REGL(env->gregs[n - 8]);
+ GET_REGL(env->gregs[n]);
} else if (n >= 25 && n < 41) {
GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
} else if (n >= 43 && n < 51) {
}
return 4;
} else if (n < 16) {
- env->gregs[n - 8] = tmp;
+ env->gregs[n] = tmp;
return 4;
} else if (n >= 25 && n < 41) {
env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
+ return 4;
} else if (n >= 43 && n < 51) {
env->gregs[n - 43] = tmp;
return 4;
return 4;
}
switch (n) {
- case 16: env->pc = tmp;
- case 17: env->pr = tmp;
- case 18: env->gbr = tmp;
- case 19: env->vbr = tmp;
- case 20: env->mach = tmp;
- case 21: env->macl = tmp;
- case 22: env->sr = tmp;
- case 23: env->fpul = tmp;
- case 24: env->fpscr = tmp;
- case 41: env->ssr = tmp;
- case 42: env->spc = tmp;
+ case 16: env->pc = tmp; break;
+ case 17: env->pr = tmp; break;
+ case 18: env->gbr = tmp; break;
+ case 19: env->vbr = tmp; break;
+ case 20: env->mach = tmp; break;
+ case 21: env->macl = tmp; break;
+ case 22: env->sr = tmp; break;
+ case 23: env->fpul = tmp; break;
+ case 24: env->fpscr = tmp; break;
+ case 41: env->ssr = tmp; break;
+ case 42: env->spc = tmp; break;
default: return 0;
}
#define NUM_CORE_REGS 49
+static int
+read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 15) {
+ GET_REG32(env->regs[n]);
+ }
+
+ if (n == 15) {
+ GET_REG32(env->pc);
+ }
+
+ if (n < 32) {
+ switch (n) {
+ case 16:
+ GET_REG8(env->pregs[n - 16]);
+ break;
+ case 17:
+ GET_REG8(env->pregs[n - 16]);
+ break;
+ case 20:
+ case 21:
+ GET_REG16(env->pregs[n - 16]);
+ break;
+ default:
+ if (n >= 23) {
+ GET_REG32(env->pregs[n - 16]);
+ }
+ break;
+ }
+ }
+ return 0;
+}
+
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
{
uint8_t srs;
+ if (env->pregs[PR_VR] < 32)
+ return read_register_crisv10(env, mem_buf, n);
+
srs = env->pregs[PR_SRS];
if (n < 16) {
GET_REG32(env->regs[n]);
}
#elif defined (TARGET_ALPHA)
-#define NUM_CORE_REGS 65
+#define NUM_CORE_REGS 67
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
{
- if (n < 31) {
- GET_REGL(env->ir[n]);
- }
- else if (n == 31) {
- GET_REGL(0);
- }
- else if (n<63) {
- uint64_t val;
+ uint64_t val;
+ CPU_DoubleU d;
- val = *((uint64_t *)&env->fir[n-32]);
- GET_REGL(val);
- }
- else if (n==63) {
- GET_REGL(env->fpcr);
- }
- else if (n==64) {
- GET_REGL(env->pc);
- }
- else {
- GET_REGL(0);
+ switch (n) {
+ case 0 ... 30:
+ val = env->ir[n];
+ break;
+ case 32 ... 62:
+ d.d = env->fir[n - 32];
+ val = d.ll;
+ break;
+ case 63:
+ val = cpu_alpha_load_fpcr(env);
+ break;
+ case 64:
+ val = env->pc;
+ break;
+ case 66:
+ val = env->unique;
+ break;
+ case 31:
+ case 65:
+ /* 31 really is the zero register; 65 is unassigned in the
+ gdb protocol, but is still required to occupy 8 bytes. */
+ val = 0;
+ break;
+ default:
+ return 0;
}
-
- return 0;
+ GET_REGL(val);
}
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
{
- target_ulong tmp;
- tmp = ldtul_p(mem_buf);
+ target_ulong tmp = ldtul_p(mem_buf);
+ CPU_DoubleU d;
- if (n < 31) {
+ switch (n) {
+ case 0 ... 30:
env->ir[n] = tmp;
+ break;
+ case 32 ... 62:
+ d.ll = tmp;
+ env->fir[n - 32] = d.d;
+ break;
+ case 63:
+ cpu_alpha_store_fpcr(env, tmp);
+ break;
+ case 64:
+ env->pc = tmp;
+ break;
+ case 66:
+ env->unique = tmp;
+ break;
+ case 31:
+ case 65:
+ /* 31 really is the zero register; 65 is unassigned in the
+ gdb protocol, but is still required to occupy 8 bytes. */
+ break;
+ default:
+ return 0;
}
-
- if (n > 31 && n < 63) {
- env->fir[n - 32] = ldfl_p(mem_buf);
- }
-
- if (n == 64 ) {
- env->pc=tmp;
- }
-
return 8;
}
#elif defined (TARGET_S390X)
/* XXX */
break;
case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
- case S390_CC_REGNUM: GET_REG32(env->cc); break;
+ case S390_CC_REGNUM:
+ env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
+ env->cc_vr);
+ GET_REG32(env->cc_op);
+ break;
}
return 0;
/* XXX */
break;
case S390_PC_REGNUM: env->psw.addr = tmpl; break;
- case S390_CC_REGNUM: env->cc = tmp32; r=4; break;
+ case S390_CC_REGNUM: env->cc_op = tmp32; r=4; break;
}
return r;
}
+#elif defined (TARGET_LM32)
+
+#include "hw/lm32_pic.h"
+#define NUM_CORE_REGS (32 + 7)
+
+static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ GET_REG32(env->regs[n]);
+ } else {
+ switch (n) {
+ case 32:
+ GET_REG32(env->pc);
+ break;
+ /* FIXME: put in right exception ID */
+ case 33:
+ GET_REG32(0);
+ break;
+ case 34:
+ GET_REG32(env->eba);
+ break;
+ case 35:
+ GET_REG32(env->deba);
+ break;
+ case 36:
+ GET_REG32(env->ie);
+ break;
+ case 37:
+ GET_REG32(lm32_pic_get_im(env->pic_state));
+ break;
+ case 38:
+ GET_REG32(lm32_pic_get_ip(env->pic_state));
+ break;
+ }
+ }
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+
+ if (n > NUM_CORE_REGS) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 32) {
+ env->regs[n] = tmp;
+ } else {
+ switch (n) {
+ case 32:
+ env->pc = tmp;
+ break;
+ case 34:
+ env->eba = tmp;
+ break;
+ case 35:
+ env->deba = tmp;
+ break;
+ case 36:
+ env->ie = tmp;
+ break;
+ case 37:
+ lm32_pic_set_im(env->pic_state, tmp);
+ break;
+ case 38:
+ lm32_pic_set_ip(env->pic_state, tmp);
+ break;
+ }
+ }
+ return 4;
+}
+#elif defined(TARGET_XTENSA)
+
+/* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
+ * Use num_regs to see all registers. gdb modification is required for that:
+ * reset bit 0 in the 'flags' field of the registers definitions in the
+ * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
+ */
+#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
+#define num_g_regs NUM_CORE_REGS
+
+static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+{
+ const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
+
+ if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
+ return 0;
+ }
+
+ switch (reg->type) {
+ case 9: /*pc*/
+ GET_REG32(env->pc);
+ break;
+
+ case 1: /*ar*/
+ xtensa_sync_phys_from_window(env);
+ GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
+ break;
+
+ case 2: /*SR*/
+ GET_REG32(env->sregs[reg->targno & 0xff]);
+ break;
+
+ case 3: /*UR*/
+ GET_REG32(env->uregs[reg->targno & 0xff]);
+ break;
+
+ case 8: /*a*/
+ GET_REG32(env->regs[reg->targno & 0x0f]);
+ break;
+
+ default:
+ qemu_log("%s from reg %d of unsupported type %d\n",
+ __func__, n, reg->type);
+ return 0;
+ }
+}
+
+static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+ const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
+
+ if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ switch (reg->type) {
+ case 9: /*pc*/
+ env->pc = tmp;
+ break;
+
+ case 1: /*ar*/
+ env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
+ xtensa_sync_window_from_phys(env);
+ break;
+
+ case 2: /*SR*/
+ env->sregs[reg->targno & 0xff] = tmp;
+ break;
+
+ case 3: /*UR*/
+ env->uregs[reg->targno & 0xff] = tmp;
+ break;
+
+ case 8: /*a*/
+ env->regs[reg->targno & 0x0f] = tmp;
+ break;
+
+ default:
+ qemu_log("%s to reg %d of unsupported type %d\n",
+ __func__, n, reg->type);
+ return 0;
+ }
+
+ return 4;
+}
#else
#define NUM_CORE_REGS 0
#endif
+#if !defined(TARGET_XTENSA)
static int num_g_regs = NUM_CORE_REGS;
+#endif
#ifdef GDB_CORE_XML
/* Encode data using the encoding for 'x' packets. */
static const char *get_feature_xml(const char *p, const char **newp)
{
- extern const char *const xml_builtin[][2];
size_t len;
int i;
const char *name;
return 0;
}
+#if !defined(TARGET_XTENSA)
/* Register a supplemental set of CPU registers. If g_pos is nonzero it
specifies the first register number and these registers are included in
a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
GDBRegisterState **p;
static int last_reg = NUM_CORE_REGS;
- s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
+ s = (GDBRegisterState *)g_malloc0(sizeof(GDBRegisterState));
s->base_reg = last_reg;
s->num_regs = num_regs;
s->get_reg = get_reg;
}
}
}
+#endif
#ifndef CONFIG_USER_ONLY
static const int xlat_gdb_type[] = {
#elif defined (TARGET_SH4)
s->c_cpu->pc = pc;
#elif defined (TARGET_MIPS)
- s->c_cpu->active_tc.PC = pc;
+ s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
+ if (pc & 1) {
+ s->c_cpu->hflags |= MIPS_HFLAG_M16;
+ } else {
+ s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
+ }
#elif defined (TARGET_MICROBLAZE)
s->c_cpu->sregs[SR_PC] = pc;
#elif defined (TARGET_CRIS)
#elif defined (TARGET_S390X)
cpu_synchronize_state(s->c_cpu);
s->c_cpu->psw.addr = pc;
+#elif defined (TARGET_LM32)
+ s->c_cpu->pc = pc;
+#elif defined(TARGET_XTENSA)
+ s->c_cpu->pc = pc;
#endif
}
case 'D':
/* Detach packet */
gdb_breakpoint_remove_all();
+ gdb_syscall_mode = GDB_SYS_DISABLED;
gdb_continue(s);
put_packet(s, "OK");
break;
break;
case 'g':
cpu_synchronize_state(s->g_cpu);
+ env = s->g_cpu;
len = 0;
for (addr = 0; addr < num_g_regs; addr++) {
reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
break;
case 'G':
cpu_synchronize_state(s->g_cpu);
+ env = s->g_cpu;
registers = mem_buf;
len = strlen(p) / 2;
hextomem((uint8_t *)registers, p, len);
if (*p == ',')
p++;
len = strtoull(p, NULL, 16);
- if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
+ if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
put_packet (s, "E14");
} else {
memtohex(buf, mem_buf, len);
if (*p == ':')
p++;
hextomem(mem_buf, p, len);
- if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
+ if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) {
put_packet(s, "E14");
- else
+ } else {
put_packet(s, "OK");
+ }
break;
case 'p':
/* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
hextomem(mem_buf, p + 5, len);
len = len / 2;
mem_buf[len++] = 0;
- qemu_chr_read(s->mon_chr, mem_buf, len);
+ qemu_chr_be_write(s->mon_chr, mem_buf, len);
put_packet(s, "OK");
break;
}
}
#ifndef CONFIG_USER_ONLY
-static void gdb_vm_state_change(void *opaque, int running, int reason)
+static void gdb_vm_state_change(void *opaque, int running, RunState state)
{
GDBState *s = gdbserver_state;
CPUState *env = s->c_cpu;
const char *type;
int ret;
- if (running || (reason != EXCP_DEBUG && reason != EXCP_INTERRUPT) ||
- s->state == RS_INACTIVE || s->state == RS_SYSCALL)
+ if (running || s->state == RS_INACTIVE || s->state == RS_SYSCALL) {
return;
-
- /* disable single step if it was enable */
- cpu_single_step(env, 0);
-
- if (reason == EXCP_DEBUG) {
+ }
+ switch (state) {
+ case RSTATE_DEBUG:
if (env->watchpoint_hit) {
switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
case BP_MEM_READ:
"T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
GDB_SIGNAL_TRAP, gdb_id(env), type,
env->watchpoint_hit->vaddr);
- put_packet(s, buf);
env->watchpoint_hit = NULL;
- return;
+ goto send_packet;
}
- tb_flush(env);
+ tb_flush(env);
ret = GDB_SIGNAL_TRAP;
- } else {
+ break;
+ case RSTATE_PAUSED:
ret = GDB_SIGNAL_INT;
+ break;
+ case RSTATE_SHUTDOWN:
+ ret = GDB_SIGNAL_QUIT;
+ break;
+ case RSTATE_IO_ERROR:
+ ret = GDB_SIGNAL_IO;
+ break;
+ case RSTATE_WATCHDOG:
+ ret = GDB_SIGNAL_ALRM;
+ break;
+ case RSTATE_PANICKED:
+ ret = GDB_SIGNAL_ABRT;
+ break;
+ case RSTATE_SAVEVM:
+ case RSTATE_RESTORE:
+ return;
+ case RSTATE_PRE_MIGRATE:
+ ret = GDB_SIGNAL_XCPU;
+ break;
+ default:
+ ret = GDB_SIGNAL_UNKNOWN;
+ break;
}
snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
+
+send_packet:
put_packet(s, buf);
+
+ /* disable single step if it was enabled */
+ cpu_single_step(env, 0);
}
#endif
gdb_current_syscall_cb = cb;
s->state = RS_SYSCALL;
#ifndef CONFIG_USER_ONLY
- vm_stop(EXCP_DEBUG);
+ vm_stop(RSTATE_DEBUG);
#endif
s->state = RS_IDLE;
va_start(va, fmt);
if (ch != '$')
return;
}
- if (vm_running) {
+ if (runstate_is_running()) {
/* when the CPU is running, we cannot do anything except stop
it when receiving a char */
- vm_stop(EXCP_INTERRUPT);
+ vm_stop(RSTATE_PAUSED);
} else
#endif
{
}
}
+/* Tell the remote gdb that the process has exited. */
+void gdb_exit(CPUState *env, int code)
+{
+ GDBState *s;
+ char buf[4];
+
+ s = gdbserver_state;
+ if (!s) {
+ return;
+ }
+#ifdef CONFIG_USER_ONLY
+ if (gdbserver_fd < 0 || s->fd < 0) {
+ return;
+ }
+#endif
+
+ snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
+ put_packet(s, buf);
+
+#ifndef CONFIG_USER_ONLY
+ if (s->chr) {
+ qemu_chr_delete(s->chr);
+ }
+#endif
+}
+
#ifdef CONFIG_USER_ONLY
int
gdb_queuesig (void)
return sig;
}
-/* Tell the remote gdb that the process has exited. */
-void gdb_exit(CPUState *env, int code)
-{
- GDBState *s;
- char buf[4];
-
- s = gdbserver_state;
- if (gdbserver_fd < 0 || s->fd < 0)
- return;
-
- snprintf(buf, sizeof(buf), "W%02x", code);
- put_packet(s, buf);
-}
-
/* Tell the remote gdb that the process has exited due to SIG. */
void gdb_signalled(CPUState *env, int sig)
{
val = 1;
setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
- s = qemu_mallocz(sizeof(GDBState));
+ s = g_malloc0(sizeof(GDBState));
s->c_cpu = first_cpu;
s->g_cpu = first_cpu;
s->fd = fd;
{
switch (event) {
case CHR_EVENT_OPENED:
- vm_stop(EXCP_INTERRUPT);
+ vm_stop(RSTATE_PAUSED);
gdb_has_xml = 0;
break;
default:
#ifndef _WIN32
static void gdb_sigterm_handler(int signal)
{
- if (vm_running)
- vm_stop(EXCP_INTERRUPT);
+ if (runstate_is_running()) {
+ vm_stop(RSTATE_PAUSED);
+ }
}
#endif
sigaction(SIGINT, &act, NULL);
}
#endif
- chr = qemu_chr_open("gdb", device, NULL);
+ chr = qemu_chr_new("gdb", device, NULL);
if (!chr)
return -1;
s = gdbserver_state;
if (!s) {
- s = qemu_mallocz(sizeof(GDBState));
+ s = g_malloc0(sizeof(GDBState));
gdbserver_state = s;
qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
/* Initialize a monitor terminal for gdb */
- mon_chr = qemu_mallocz(sizeof(*mon_chr));
+ mon_chr = g_malloc0(sizeof(*mon_chr));
mon_chr->chr_write = gdb_monitor_write;
monitor_init(mon_chr, 0);
} else {
if (s->chr)
- qemu_chr_close(s->chr);
+ qemu_chr_delete(s->chr);
mon_chr = s->mon_chr;
memset(s, 0, sizeof(GDBState));
}
projects / qemu.git / blobdiff