* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "hw.h"
-#include "qemu-timer.h"
-#include "net.h"
+#include "qemu/timer.h"
+#include "net/net.h"
#include "mips.h"
//#define DEBUG_SONIC
#endif
QEMUTimer *watchdog;
int64_t wt_last_update;
- VLANClientState *vc;
- int mmio_index;
+ NICConf conf;
+ NICState *nic;
+ MemoryRegion *address_space;
+ MemoryRegion mmio;
/* Registers */
uint8_t cam[16][6];
int loopback_packet;
/* Memory access */
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
}
ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
- s->wt_last_update = qemu_get_clock(vm_clock);
- delay = ticks_per_sec * ticks / 5000000;
+ s->wt_last_update = qemu_get_clock_ns(vm_clock);
+ delay = get_ticks_per_sec() * ticks / 5000000;
qemu_mod_timer(s->watchdog, s->wt_last_update + delay);
}
return;
}
- elapsed = s->wt_last_update - qemu_get_clock(vm_clock);
+ elapsed = s->wt_last_update - qemu_get_clock_ns(vm_clock);
val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
val -= elapsed / 5000000;
s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
/* Loopback */
s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
- if (s->vc->can_receive(s->vc)) {
+ if (s->nic->nc.info->can_receive(&s->nic->nc)) {
s->loopback_packet = 1;
- s->vc->receive(s->vc, s->tx_buffer, tx_len);
+ s->nic->nc.info->receive(&s->nic->nc, s->tx_buffer, tx_len);
}
} else {
/* Transmit packet */
- qemu_send_packet(s->vc, s->tx_buffer, tx_len);
+ qemu_send_packet(&s->nic->nc, s->tx_buffer, tx_len);
}
s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
switch (reg) {
/* Command register */
case SONIC_CR:
- do_command(s, val);;
+ do_command(s, val);
break;
/* Prevent write to read-only registers */
case SONIC_CAP2:
dp8393x_update_irq(s);
}
-static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readw(void *opaque, hwaddr addr)
{
dp8393xState *s = opaque;
int reg;
return read_register(s, reg);
}
-static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readb(void *opaque, hwaddr addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readl(void *opaque, hwaddr addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
return v;
}
-static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writew(void *opaque, hwaddr addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
write_register(s, reg, (uint16_t)val);
}
-static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
dp8393x_writew(opaque, addr & ~0x1, val);
}
-static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writel(void *opaque, hwaddr addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
}
-static CPUReadMemoryFunc *dp8393x_read[3] = {
- dp8393x_readb,
- dp8393x_readw,
- dp8393x_readl,
+static const MemoryRegionOps dp8393x_ops = {
+ .old_mmio = {
+ .read = { dp8393x_readb, dp8393x_readw, dp8393x_readl, },
+ .write = { dp8393x_writeb, dp8393x_writew, dp8393x_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc *dp8393x_write[3] = {
- dp8393x_writeb,
- dp8393x_writew,
- dp8393x_writel,
-};
-
-static int nic_can_receive(VLANClientState *vc)
+static int nic_can_receive(NetClientState *nc)
{
- dp8393xState *s = vc->opaque;
+ dp8393xState *s = DO_UPCAST(NICState, nc, nc)->opaque;
if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
return 0;
return -1;
}
-static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size)
+static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size)
{
+ dp8393xState *s = DO_UPCAST(NICState, nc, nc)->opaque;
uint16_t data[10];
- dp8393xState *s = vc->opaque;
int packet_type;
uint32_t available, address;
int width, rx_len = size;
dp8393x_update_irq(s);
}
-static void nic_cleanup(VLANClientState *vc)
+static void nic_cleanup(NetClientState *nc)
{
- dp8393xState *s = vc->opaque;
+ dp8393xState *s = DO_UPCAST(NICState, nc, nc)->opaque;
- cpu_unregister_io_memory(s->mmio_index);
+ memory_region_del_subregion(s->address_space, &s->mmio);
+ memory_region_destroy(&s->mmio);
qemu_del_timer(s->watchdog);
qemu_free_timer(s->watchdog);
- qemu_free(s);
+ g_free(s);
}
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+static NetClientInfo net_dp83932_info = {
+ .type = NET_CLIENT_OPTIONS_KIND_NIC,
+ .size = sizeof(NICState),
+ .can_receive = nic_can_receive,
+ .receive = nic_receive,
+ .cleanup = nic_cleanup,
+};
+
+void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
+ MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
qemu_check_nic_model(nd, "dp83932");
- s = qemu_mallocz(sizeof(dp8393xState));
+ s = g_malloc0(sizeof(dp8393xState));
+ s->address_space = address_space;
s->mem_opaque = mem_opaque;
s->memory_rw = memory_rw;
s->it_shift = it_shift;
s->irq = irq;
- s->watchdog = qemu_new_timer(vm_clock, dp8393x_watchdog, s);
+ s->watchdog = qemu_new_timer_ns(vm_clock, dp8393x_watchdog, s);
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
- s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
- nic_can_receive, nic_receive, NULL,
- nic_cleanup, s);
+ s->conf.macaddr = nd->macaddr;
+ s->conf.peer = nd->netdev;
+
+ s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s);
- qemu_format_nic_info_str(s->vc, nd->macaddr);
+ qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
qemu_register_reset(nic_reset, s);
nic_reset(s);
- s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
- cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
+ memory_region_init_io(&s->mmio, &dp8393x_ops, s,
+ "dp8393x", 0x40 << it_shift);
+ memory_region_add_subregion(address_space, base, &s->mmio);
}
projects / qemu.git / blobdiff