#include "isa.h"
#include "pc.h"
#include "qemu-timer.h"
+#include "sysemu.h"
//#define DEBUG_SERIAL
#define RECV_FIFO 1
#define MAX_XMIT_RETRY 4
+#ifdef DEBUG_SERIAL
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do {} while (0)
+#endif
+
typedef struct SerialFIFO {
uint8_t data[UART_FIFO_LENGTH];
uint8_t count;
int poll_msl;
struct QEMUTimer *modem_status_poll;
+ MemoryRegion io;
};
typedef struct ISASerialState {
ISADevice dev;
+ uint32_t index;
uint32_t iobase;
uint32_t isairq;
SerialState state;
{
SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
- f->data[f->head++] = chr;
+ /* Receive overruns do not overwrite FIFO contents. */
+ if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
+
+ f->data[f->head++] = chr;
+
+ if (f->head == UART_FIFO_LENGTH)
+ f->head = 0;
+ }
- if (f->head == UART_FIFO_LENGTH)
- f->head = 0;
- f->count++;
+ if (f->count < UART_FIFO_LENGTH)
+ f->count++;
+ else if (fifo == RECV_FIFO)
+ s->lsr |= UART_LSR_OE;
return 1;
}
if (s->divider == 0)
return;
+ /* Start bit. */
frame_size = 1;
if (s->lcr & 0x08) {
+ /* Parity bit. */
+ frame_size++;
if (s->lcr & 0x10)
parity = 'E';
else
parity = 'O';
} else {
parity = 'N';
- frame_size = 0;
}
if (s->lcr & 0x04)
stop_bits = 2;
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
- qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
-#if 0
- printf("speed=%d parity=%c data=%d stop=%d\n",
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
+
+ DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
speed, parity, data_bits, stop_bits);
-#endif
}
static void serial_update_msl(SerialState *s)
qemu_del_timer(s->modem_status_poll);
- if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
+ if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
s->poll_msl = -1;
return;
}
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
if (s->poll_msl)
- qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
+ qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
}
static void serial_xmit(void *opaque)
{
SerialState *s = opaque;
- uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
+ uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
if (s->tsr_retry <= 0) {
if (s->fcr & UART_FCR_FE) {
if (s->mcr & UART_MCR_LOOP) {
/* in loopback mode, say that we just received a char */
serial_receive1(s, &s->tsr, 1);
- } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
+ } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
s->tsr_retry++;
qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time);
s->tsr_retry = 0;
}
- s->last_xmit_ts = qemu_get_clock(vm_clock);
+ s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
if (!(s->lsr & UART_LSR_THRE))
qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
SerialState *s = opaque;
addr &= 7;
-#ifdef DEBUG_SERIAL
- printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
-#endif
+ DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
switch(addr) {
default:
case 0:
} else {
s->thr = (uint8_t) val;
if(s->fcr & UART_FCR_FE) {
- fifo_put(s, XMIT_FIFO, s->thr);
- s->thr_ipending = 0;
- s->lsr &= ~UART_LSR_TEMT;
- s->lsr &= ~UART_LSR_THRE;
- serial_update_irq(s);
+ fifo_put(s, XMIT_FIFO, s->thr);
+ s->thr_ipending = 0;
+ s->lsr &= ~UART_LSR_TEMT;
+ s->lsr &= ~UART_LSR_THRE;
+ serial_update_irq(s);
} else {
- s->thr_ipending = 0;
- s->lsr &= ~UART_LSR_THRE;
- serial_update_irq(s);
+ s->thr_ipending = 0;
+ s->lsr &= ~UART_LSR_THRE;
+ serial_update_irq(s);
}
serial_xmit(s);
}
break_enable = (val >> 6) & 1;
if (break_enable != s->last_break_enable) {
s->last_break_enable = break_enable;
- qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable);
}
}
if (s->poll_msl >= 0 && old_mcr != s->mcr) {
- qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
+ qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
if (val & UART_MCR_DTR)
flags |= CHR_TIOCM_DTR;
- qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
+ qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
/* Update the modem status after a one-character-send wait-time, since there may be a response
from the device/computer at the other end of the serial line */
- qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
+ qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
}
}
break;
if (s->recv_fifo.count == 0)
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
else
- qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
+ qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
s->timeout_ipending = 0;
} else {
ret = s->rbr;
break;
case 2:
ret = s->iir;
+ if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
s->thr_ipending = 0;
- serial_update_irq(s);
+ serial_update_irq(s);
+ }
break;
case 3:
ret = s->lcr;
break;
case 5:
ret = s->lsr;
- /* Clear break interrupt */
- if (s->lsr & UART_LSR_BI) {
- s->lsr &= ~UART_LSR_BI;
+ /* Clear break and overrun interrupts */
+ if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
+ s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
serial_update_irq(s);
}
break;
ret = s->scr;
break;
}
-#ifdef DEBUG_SERIAL
- printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
-#endif
+ DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
return ret;
}
}
s->lsr |= UART_LSR_DR;
/* call the timeout receive callback in 4 char transmit time */
- qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
+ qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
} else {
+ if (s->lsr & UART_LSR_DR)
+ s->lsr |= UART_LSR_OE;
s->rbr = buf[0];
s->lsr |= UART_LSR_DR;
}
static void serial_event(void *opaque, int event)
{
SerialState *s = opaque;
-#ifdef DEBUG_SERIAL
- printf("serial: event %x\n", event);
-#endif
+ DPRINTF("event %x\n", event);
if (event == CHR_EVENT_BREAK)
serial_receive_break(s);
}
s->fcr_vmstate = s->fcr;
}
-static int serial_pre_load(void *opaque)
-{
- SerialState *s = opaque;
- s->fcr_vmstate = 0;
- return 0;
-}
-
static int serial_post_load(void *opaque, int version_id)
{
SerialState *s = opaque;
+ if (version_id < 3) {
+ s->fcr_vmstate = 0;
+ }
/* Initialize fcr via setter to perform essential side-effects */
serial_ioport_write(s, 0x02, s->fcr_vmstate);
+ serial_update_parameters(s);
return 0;
}
.version_id = 3,
.minimum_version_id = 2,
.pre_save = serial_pre_save,
- .pre_load = serial_pre_load,
.post_load = serial_post_load,
.fields = (VMStateField []) {
VMSTATE_UINT16_V(divider, SerialState, 2),
s->lcr = 0;
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
- /* Default to 9600 baud, no parity, one stop bit */
+ /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
s->divider = 0x0C;
s->mcr = UART_MCR_OUT2;
s->scr = 0;
s->tsr_retry = 0;
- s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9;
+ s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
s->poll_msl = 0;
fifo_clear(s,RECV_FIFO);
fifo_clear(s,XMIT_FIFO);
- s->last_xmit_ts = qemu_get_clock(vm_clock);
+ s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
s->thr_ipending = 0;
s->last_break_enable = 0;
exit(1);
}
- s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
+ s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
- s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
- s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
+ s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
+ s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s);
qemu_register_reset(serial_reset, s);
- serial_reset(s);
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
serial_event, s);
}
+/* Change the main reference oscillator frequency. */
+void serial_set_frequency(SerialState *s, uint32_t frequency)
+{
+ s->baudbase = frequency;
+ serial_update_parameters(s);
+}
+
+static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
+static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
+
+static const MemoryRegionPortio serial_portio[] = {
+ { 0, 8, 1, .read = serial_ioport_read, .write = serial_ioport_write },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps serial_io_ops = {
+ .old_portio = serial_portio
+};
+
static int serial_isa_initfn(ISADevice *dev)
{
+ static int index;
ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
SerialState *s = &isa->state;
+ if (isa->index == -1)
+ isa->index = index;
+ if (isa->index >= MAX_SERIAL_PORTS)
+ return -1;
+ if (isa->iobase == -1)
+ isa->iobase = isa_serial_io[isa->index];
+ if (isa->isairq == -1)
+ isa->isairq = isa_serial_irq[isa->index];
+ index++;
+
s->baudbase = 115200;
isa_init_irq(dev, &s->irq, isa->isairq);
serial_init_core(s);
- vmstate_register(isa->iobase, &vmstate_serial, s);
+ qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
- register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
- register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
+ memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
+ isa_register_ioport(dev, &s->io, isa->iobase);
return 0;
}
-static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
-static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
-
-SerialState *serial_isa_init(int index, CharDriverState *chr)
-{
- ISADevice *dev;
-
- dev = isa_create("isa-serial");
- qdev_prop_set_uint32(&dev->qdev, "iobase", isa_serial_io[index]);
- qdev_prop_set_uint32(&dev->qdev, "irq", isa_serial_irq[index]);
- qdev_prop_set_chr(&dev->qdev, "chardev", chr);
- if (qdev_init(&dev->qdev) != 0)
- return NULL;
- return &DO_UPCAST(ISASerialState, dev, dev)->state;
-}
+static const VMStateDescription vmstate_isa_serial = {
+ .name = "serial",
+ .version_id = 3,
+ .minimum_version_id = 2,
+ .fields = (VMStateField []) {
+ VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
+ VMSTATE_END_OF_LIST()
+ }
+};
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr)
{
SerialState *s;
- s = qemu_mallocz(sizeof(SerialState));
+ s = g_malloc0(sizeof(SerialState));
s->irq = irq;
s->baudbase = baudbase;
s->chr = chr;
serial_init_core(s);
- vmstate_register(base, &vmstate_serial, s);
+ vmstate_register(NULL, base, &vmstate_serial, s);
register_ioport_write(base, 8, 1, serial_ioport_write, s);
register_ioport_read(base, 8, 1, serial_ioport_read, s);
}
/* Memory mapped interface */
-static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
-{
- SerialState *s = opaque;
-
- return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
-}
-
-static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- SerialState *s = opaque;
-
- serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
-}
-
-static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
-{
- SerialState *s = opaque;
- uint32_t val;
-
- val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
- return val;
-}
-
-static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- SerialState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
- value = bswap16(value);
-#endif
- serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
-}
-
-static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
SerialState *s = opaque;
- uint32_t val;
-
- val = serial_ioport_read(s, addr >> s->it_shift);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- return val;
+ return serial_ioport_read(s, addr >> s->it_shift);
}
-static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void serial_mm_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
{
SerialState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
- value = bswap32(value);
-#endif
+ value &= ~0u >> (32 - (size * 8));
serial_ioport_write(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc * const serial_mm_read[] = {
- &serial_mm_readb,
- &serial_mm_readw,
- &serial_mm_readl,
-};
-
-static CPUWriteMemoryFunc * const serial_mm_write[] = {
- &serial_mm_writeb,
- &serial_mm_writew,
- &serial_mm_writel,
+static const MemoryRegionOps serial_mm_ops[3] = {
+ [DEVICE_NATIVE_ENDIAN] = {
+ .read = serial_mm_read,
+ .write = serial_mm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ },
+ [DEVICE_LITTLE_ENDIAN] = {
+ .read = serial_mm_read,
+ .write = serial_mm_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ },
+ [DEVICE_BIG_ENDIAN] = {
+ .read = serial_mm_read,
+ .write = serial_mm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ },
};
-SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
- qemu_irq irq, int baudbase,
- CharDriverState *chr, int ioregister)
+SerialState *serial_mm_init(MemoryRegion *address_space,
+ target_phys_addr_t base, int it_shift,
+ qemu_irq irq, int baudbase,
+ CharDriverState *chr, enum device_endian end)
{
SerialState *s;
- int s_io_memory;
- s = qemu_mallocz(sizeof(SerialState));
+ s = g_malloc0(sizeof(SerialState));
s->it_shift = it_shift;
s->irq = irq;
s->chr = chr;
serial_init_core(s);
- vmstate_register(base, &vmstate_serial, s);
+ vmstate_register(NULL, base, &vmstate_serial, s);
+
+ memory_region_init_io(&s->io, &serial_mm_ops[end], s,
+ "serial", 8 << it_shift);
+ memory_region_add_subregion(address_space, base, &s->io);
- if (ioregister) {
- s_io_memory = cpu_register_io_memory(serial_mm_read,
- serial_mm_write, s);
- cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
- }
serial_update_msl(s);
return s;
}
static ISADeviceInfo serial_isa_info = {
.qdev.name = "isa-serial",
.qdev.size = sizeof(ISASerialState),
+ .qdev.vmsd = &vmstate_isa_serial,
.init = serial_isa_initfn,
.qdev.props = (Property[]) {
- DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, 0x3f8),
- DEFINE_PROP_UINT32("irq", ISASerialState, isairq, 4),
+ DEFINE_PROP_UINT32("index", ISASerialState, index, -1),
+ DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, -1),
+ DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1),
DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
DEFINE_PROP_END_OF_LIST(),
},
projects / qemu.git / blobdiff