#ifndef HW_VFIO_VFIO_PCI_H
#define HW_VFIO_VFIO_PCI_H
-#include "qemu-common.h"
#include "exec/memory.h"
#include "hw/pci/pci.h"
#include "hw/vfio/vfio-common.h"
struct VFIOPCIDevice;
+typedef struct VFIOIOEventFD {
+ QLIST_ENTRY(VFIOIOEventFD) next;
+ MemoryRegion *mr;
+ hwaddr addr;
+ unsigned size;
+ uint64_t data;
+ EventNotifier e;
+ VFIORegion *region;
+ hwaddr region_addr;
+ bool dynamic; /* Added runtime, removed on device reset */
+ bool vfio;
+} VFIOIOEventFD;
+
typedef struct VFIOQuirk {
QLIST_ENTRY(VFIOQuirk) next;
void *data;
+ QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
int nr_mem;
MemoryRegion *mem;
+ void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk);
} VFIOQuirk;
typedef struct VFIOBAR {
#define VFIO_FEATURE_ENABLE_IGD_OPREGION \
(1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
OnOffAuto display;
+ uint32_t display_xres;
+ uint32_t display_yres;
int32_t bootindex;
uint32_t igd_gms;
OffAutoPCIBAR msix_relo;
bool no_kvm_msi;
bool no_kvm_msix;
bool no_geforce_quirks;
+ bool no_kvm_ioeventfd;
+ bool no_vfio_ioeventfd;
+ bool enable_ramfb;
+ VFIODisplay *dpy;
} VFIOPCIDevice;
uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
+void vfio_quirk_reset(VFIOPCIDevice *vdev);
extern const PropertyInfo qdev_prop_nv_gpudirect_clique;
int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
struct vfio_region_info *info,
Error **errp);
+int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp);
+int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp);
+void vfio_display_reset(VFIOPCIDevice *vdev);
int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
void vfio_display_finalize(VFIOPCIDevice *vdev);