#include "qemu-common.h"
#include "hw/arm/fsl-imx6.h"
#include "sysemu/sysemu.h"
-#include "sysemu/char.h"
+#include "chardev/char.h"
#include "qemu/error-report.h"
+#define IMX6_ESDHC_CAPABILITIES 0x057834b4
+
#define NAME_SIZE 20
static void fsl_imx6_init(Object *obj)
object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL);
}
- object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
+ object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL);
}
for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
- object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_SYSBUS_SDHCI);
+ object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_IMX_USDHC);
qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL);
};
if (i < MAX_SERIAL_PORTS) {
- CharDriverState *chr;
+ Chardev *chr;
chr = serial_hds[i];
if (!chr) {
char *label = g_strdup_printf("imx6.uart%d", i + 1);
- chr = qemu_chr_new(label, "null", NULL);
+ chr = qemu_chr_new(label, "null");
g_free(label);
serial_hds[i] = chr;
}
{ FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
};
+ /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
+ &err);
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
+ "capareg", &err);
object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
spi_table[i].irq));
}
+ qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
if (err) {
error_propagate(errp, err);
}
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
&s->ocram);
- vmstate_register_ram_global(&s->ocram);
/* internal OCRAM (256 KB) is aliased over 1 MB */
memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = fsl_imx6_realize;
-
- /*
- * Reason: creates an ARM CPU, thus use after free(), see
- * arm_cpu_class_init()
- */
- dc->cannot_destroy_with_object_finalize_yet = true;
dc->desc = "i.MX6 SOC";
+ /* Reason: Uses serial_hds[] in the realize() function */
+ dc->user_creatable = false;
}
static const TypeInfo fsl_imx6_type_info = {