s->init4 = val & 1;
s->single_mode = val & 2;
if (val & 0x08) {
- hw_error("level sensitive irq not supported");
+ qemu_log_mask(LOG_UNIMP,
+ "i8259: level sensitive irq not supported\n");
}
} else if (val & 0x08) {
if (val & 0x04) {
ret = s->imr;
}
}
- DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
+ DPRINTF("read: addr=0x%02" HWADDR_PRIx " val=0x%02x\n", addr, ret);
return ret;
}
ISADevice *isadev;
int i;
- irq_set = g_malloc(ISA_NUM_IRQS * sizeof(qemu_irq));
+ irq_set = g_new0(qemu_irq, ISA_NUM_IRQS);
isadev = i8259_init_chip(TYPE_I8259, bus, true);
dev = DEVICE(isadev);