iotests: Add preallocated growth test for qcow2

[qemu.git] / tests / ide-test.c

diff --git a/tests/ide-test.c b/tests/ide-test.c
index 559473812cf710ebc864fadcf64abc08753bff6b..bfd79ddbdcb8a6bcb89c00e649558cdb7124fa9a 100644 (file)
--- a/tests/ide-test.c
+++ b/tests/ide-test.c
@@ -22,11 +22,8 @@
  * THE SOFTWARE.
  */
 
  * THE SOFTWARE.
  */
 

-#include <stdint.h>
-#include <string.h>
-#include <stdio.h>
+#include "qemu/osdep.h"

 
 

-#include <glib.h>

 
 #include "libqtest.h"
 #include "libqos/libqos.h"
 
 #include "libqtest.h"
 #include "libqos/libqos.h"


@@ -34,6 +31,7 @@
 #include "libqos/malloc-pc.h"
 
 #include "qemu-common.h"
 #include "libqos/malloc-pc.h"
 
 #include "qemu-common.h"

+#include "qemu/bswap.h"

 #include "hw/pci/pci_ids.h"
 #include "hw/pci/pci_regs.h"
 
 #include "hw/pci/pci_ids.h"
 #include "hw/pci/pci_regs.h"
 


@@ -139,13 +137,13 @@ static void ide_test_quit(void)
     qtest_end();
 }
 
     qtest_end();
 }
 

-static QPCIDevice *get_pci_device(uint16_t *bmdma_base)
+static QPCIDevice *get_pci_device(QPCIBar *bmdma_bar, QPCIBar *ide_bar)

 {
     QPCIDevice *dev;
     uint16_t vendor_id, device_id;
 
     if (!pcibus) {
 {
     QPCIDevice *dev;
     uint16_t vendor_id, device_id;
 
     if (!pcibus) {

-        pcibus = qpci_init_pc();
+        pcibus = qpci_init_pc(NULL);

     }
 
     /* Find PCI device and verify it's the right one */
     }
 
     /* Find PCI device and verify it's the right one */


@@ -158,7 +156,9 @@ static QPCIDevice *get_pci_device(uint16_t *bmdma_base)
     g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);
 
     /* Map bmdma BAR */
     g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);
 
     /* Map bmdma BAR */

-    *bmdma_base = (uint16_t)(uintptr_t) qpci_iomap(dev, 4, NULL);
+    *bmdma_bar = qpci_iomap(dev, 4, NULL);
+
+    *ide_bar = qpci_legacy_iomap(dev, IDE_BASE);

 
     qpci_device_enable(dev);
 
 
     qpci_device_enable(dev);
 


@@ -181,17 +181,18 @@ typedef struct PrdtEntry {
 
 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
                             PrdtEntry *prdt, int prdt_entries,
 
 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
                             PrdtEntry *prdt, int prdt_entries,

-                            void(*post_exec)(uint64_t sector, int nb_sectors))
+                            void(*post_exec)(QPCIDevice *dev, QPCIBar ide_bar,
+                                             uint64_t sector, int nb_sectors))

 {
     QPCIDevice *dev;
 {
     QPCIDevice *dev;

-    uint16_t bmdma_base;
+    QPCIBar bmdma_bar, ide_bar;

     uintptr_t guest_prdt;
     size_t len;
     bool from_dev;
     uint8_t status;
     int flags;
 
     uintptr_t guest_prdt;
     size_t len;
     bool from_dev;
     uint8_t status;
     int flags;
 

-    dev = get_pci_device(&bmdma_base);
+    dev = get_pci_device(&bmdma_bar, &ide_bar);

 
     flags = cmd & ~0xff;
     cmd &= 0xff;
 
     flags = cmd & ~0xff;
     cmd &= 0xff;


@@ -216,59 +217,60 @@ static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
     }
 
     /* Select device 0 */
     }
 
     /* Select device 0 */

-    outb(IDE_BASE + reg_device, 0 | LBA);
+    qpci_io_writeb(dev, ide_bar, reg_device, 0 | LBA);

 
     /* Stop any running transfer, clear any pending interrupt */
 
     /* Stop any running transfer, clear any pending interrupt */

-    outb(bmdma_base + bmreg_cmd, 0);
-    outb(bmdma_base + bmreg_status, BM_STS_INTR);
+    qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);
+    qpci_io_writeb(dev, bmdma_bar, bmreg_status, BM_STS_INTR);

 
     /* Setup PRDT */
     len = sizeof(*prdt) * prdt_entries;
     guest_prdt = guest_alloc(guest_malloc, len);
     memwrite(guest_prdt, prdt, len);
 
     /* Setup PRDT */
     len = sizeof(*prdt) * prdt_entries;
     guest_prdt = guest_alloc(guest_malloc, len);
     memwrite(guest_prdt, prdt, len);

-    outl(bmdma_base + bmreg_prdt, guest_prdt);
+    qpci_io_writel(dev, bmdma_bar, bmreg_prdt, guest_prdt);

 
     /* ATA DMA command */
     if (cmd == CMD_PACKET) {
         /* Enables ATAPI DMA; otherwise PIO is attempted */
 
     /* ATA DMA command */
     if (cmd == CMD_PACKET) {
         /* Enables ATAPI DMA; otherwise PIO is attempted */

-        outb(IDE_BASE + reg_feature, 0x01);
+        qpci_io_writeb(dev, ide_bar, reg_feature, 0x01);

     } else {
     } else {

-        outb(IDE_BASE + reg_nsectors, nb_sectors);
-        outb(IDE_BASE + reg_lba_low,    sector & 0xff);
-        outb(IDE_BASE + reg_lba_middle, (sector >> 8) & 0xff);
-        outb(IDE_BASE + reg_lba_high,   (sector >> 16) & 0xff);
+        qpci_io_writeb(dev, ide_bar, reg_nsectors, nb_sectors);
+        qpci_io_writeb(dev, ide_bar, reg_lba_low,    sector & 0xff);
+        qpci_io_writeb(dev, ide_bar, reg_lba_middle, (sector >> 8) & 0xff);
+        qpci_io_writeb(dev, ide_bar, reg_lba_high,   (sector >> 16) & 0xff);

     }
 
     }
 

-    outb(IDE_BASE + reg_command, cmd);
+    qpci_io_writeb(dev, ide_bar, reg_command, cmd);

 
     if (post_exec) {
 
     if (post_exec) {

-        post_exec(sector, nb_sectors);
+        post_exec(dev, ide_bar, sector, nb_sectors);

     }
 
     /* Start DMA transfer */
     }
 
     /* Start DMA transfer */

-    outb(bmdma_base + bmreg_cmd, BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0));
+    qpci_io_writeb(dev, bmdma_bar, bmreg_cmd,
+                   BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0));

 
     if (flags & CMDF_ABORT) {
 
     if (flags & CMDF_ABORT) {

-        outb(bmdma_base + bmreg_cmd, 0);
+        qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);

     }
 
     /* Wait for the DMA transfer to complete */
     do {
     }
 
     /* Wait for the DMA transfer to complete */
     do {

-        status = inb(bmdma_base + bmreg_status);
+        status = qpci_io_readb(dev, bmdma_bar, bmreg_status);

     } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE);
 
     g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR));
 
     /* Check IDE status code */
     } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE);
 
     g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR));
 
     /* Check IDE status code */

-    assert_bit_set(inb(IDE_BASE + reg_status), DRDY);
-    assert_bit_clear(inb(IDE_BASE + reg_status), BSY | DRQ);
+    assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRDY);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), BSY | DRQ);

 
     /* Reading the status register clears the IRQ */
     g_assert(!get_irq(IDE_PRIMARY_IRQ));
 
     /* Stop DMA transfer if still active */
     if (status & BM_STS_ACTIVE) {
 
     /* Reading the status register clears the IRQ */
     g_assert(!get_irq(IDE_PRIMARY_IRQ));
 
     /* Stop DMA transfer if still active */
     if (status & BM_STS_ACTIVE) {

-        outb(bmdma_base + bmreg_cmd, 0);
+        qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);

     }
 
     free_pci_device(dev);
     }
 
     free_pci_device(dev);


@@ -278,6 +280,8 @@ static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
 
 static void test_bmdma_simple_rw(void)
 {
 
 static void test_bmdma_simple_rw(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t status;
     uint8_t *buf;
     uint8_t *cmpbuf;
     uint8_t status;
     uint8_t *buf;
     uint8_t *cmpbuf;


@@ -291,6 +295,8 @@ static void test_bmdma_simple_rw(void)
         },
     };
 
         },
     };
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+

     buf = g_malloc(len);
     cmpbuf = g_malloc(len);
 
     buf = g_malloc(len);
     cmpbuf = g_malloc(len);
 


@@ -301,7 +307,7 @@ static void test_bmdma_simple_rw(void)
     status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt,
                               ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);
     status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt,
                               ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);

 
     /* Write 0xaa pattern to sector 1 */
     memset(buf, 0xaa, len);
 
     /* Write 0xaa pattern to sector 1 */
     memset(buf, 0xaa, len);


@@ -310,14 +316,14 @@ static void test_bmdma_simple_rw(void)
     status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt,
                               ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);
     status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt,
                               ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);

 
     /* Read and verify 0x55 pattern in sector 0 */
     memset(cmpbuf, 0x55, len);
 
     status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);
 
     /* Read and verify 0x55 pattern in sector 0 */
     memset(cmpbuf, 0x55, len);
 
     status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);

 
     memread(guest_buf, buf, len);
     g_assert(memcmp(buf, cmpbuf, len) == 0);
 
     memread(guest_buf, buf, len);
     g_assert(memcmp(buf, cmpbuf, len) == 0);


@@ -327,18 +333,21 @@ static void test_bmdma_simple_rw(void)
 
     status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);
 
     status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);

 
     memread(guest_buf, buf, len);
     g_assert(memcmp(buf, cmpbuf, len) == 0);
 
 
 
     memread(guest_buf, buf, len);
     g_assert(memcmp(buf, cmpbuf, len) == 0);
 
 

+    free_pci_device(dev);

     g_free(buf);
     g_free(cmpbuf);
 }
 
 static void test_bmdma_short_prdt(void)
 {
     g_free(buf);
     g_free(cmpbuf);
 }
 
 static void test_bmdma_short_prdt(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t status;
 
     PrdtEntry prdt[] = {
     uint8_t status;
 
     PrdtEntry prdt[] = {


@@ -348,21 +357,26 @@ static void test_bmdma_short_prdt(void)
         },
     };
 
         },
     };
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+

     /* Normal request */
     status = send_dma_request(CMD_READ_DMA, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);
     /* Normal request */
     status = send_dma_request(CMD_READ_DMA, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);

 
     /* Abort the request before it completes */
     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);
 
     /* Abort the request before it completes */
     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
+    free_pci_device(dev);

 }
 
 static void test_bmdma_one_sector_short_prdt(void)
 {
 }
 
 static void test_bmdma_one_sector_short_prdt(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t status;
 
     /* Read 2 sectors but only give 1 sector in PRDT */
     uint8_t status;
 
     /* Read 2 sectors but only give 1 sector in PRDT */


@@ -373,21 +387,26 @@ static void test_bmdma_one_sector_short_prdt(void)
         },
     };
 
         },
     };
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+

     /* Normal request */
     status = send_dma_request(CMD_READ_DMA, 0, 2,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);
     /* Normal request */
     status = send_dma_request(CMD_READ_DMA, 0, 2,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);

 
     /* Abort the request before it completes */
     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);
 
     /* Abort the request before it completes */
     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, 0);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
+    free_pci_device(dev);

 }
 
 static void test_bmdma_long_prdt(void)
 {
 }
 
 static void test_bmdma_long_prdt(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t status;
 
     PrdtEntry prdt[] = {
     uint8_t status;
 
     PrdtEntry prdt[] = {


@@ -397,23 +416,30 @@ static void test_bmdma_long_prdt(void)
         },
     };
 
         },
     };
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+

     /* Normal request */
     status = send_dma_request(CMD_READ_DMA, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
     /* Normal request */
     status = send_dma_request(CMD_READ_DMA, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);

 
     /* Abort the request before it completes */
     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);
 
     /* Abort the request before it completes */
     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
                               prdt, ARRAY_SIZE(prdt), NULL);
     g_assert_cmphex(status, ==, BM_STS_INTR);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
+    free_pci_device(dev);

 }
 
 static void test_bmdma_no_busmaster(void)
 {
 }
 
 static void test_bmdma_no_busmaster(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t status;
 
     uint8_t status;
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+

     /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
      * able to access it anyway because the Bus Master bit in the PCI command
      * register isn't set. This is complete nonsense, but it used to be pretty
     /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
      * able to access it anyway because the Bus Master bit in the PCI command
      * register isn't set. This is complete nonsense, but it used to be pretty


@@ -426,7 +452,8 @@ static void test_bmdma_no_busmaster(void)
     /* Not entirely clear what the expected result is, but this is what we get
      * in practice. At least we want to be aware of any changes. */
     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
     /* Not entirely clear what the expected result is, but this is what we get
      * in practice. At least we want to be aware of any changes. */
     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);

-    assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
+    free_pci_device(dev);

 }
 
 static void test_bmdma_setup(void)
 }
 
 static void test_bmdma_setup(void)


@@ -456,6 +483,8 @@ static void string_cpu_to_be16(uint16_t *s, size_t bytes)
 
 static void test_identify(void)
 {
 
 static void test_identify(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t data;
     uint16_t buf[256];
     int i;
     uint8_t data;
     uint16_t buf[256];
     int i;


@@ -466,23 +495,25 @@ static void test_identify(void)
         "-global ide-hd.ver=%s",
         tmp_path, "testdisk", "version");
 
         "-global ide-hd.ver=%s",
         tmp_path, "testdisk", "version");
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+

     /* IDENTIFY command on device 0*/
     /* IDENTIFY command on device 0*/

-    outb(IDE_BASE + reg_device, 0);
-    outb(IDE_BASE + reg_command, CMD_IDENTIFY);
+    qpci_io_writeb(dev, ide_bar, reg_device, 0);
+    qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY);

 
     /* Read in the IDENTIFY buffer and check registers */
 
     /* Read in the IDENTIFY buffer and check registers */

-    data = inb(IDE_BASE + reg_device);
+    data = qpci_io_readb(dev, ide_bar, reg_device);

     g_assert_cmpint(data & DEV, ==, 0);
 
     for (i = 0; i < 256; i++) {
     g_assert_cmpint(data & DEV, ==, 0);
 
     for (i = 0; i < 256; i++) {

-        data = inb(IDE_BASE + reg_status);
+        data = qpci_io_readb(dev, ide_bar, reg_status);

         assert_bit_set(data, DRDY | DRQ);
         assert_bit_clear(data, BSY | DF | ERR);
 
         assert_bit_set(data, DRDY | DRQ);
         assert_bit_clear(data, BSY | DF | ERR);
 

-        ((uint16_t*) buf)[i] = inw(IDE_BASE + reg_data);
+        buf[i] = qpci_io_readw(dev, ide_bar, reg_data);

     }
 
     }
 

-    data = inb(IDE_BASE + reg_status);
+    data = qpci_io_readb(dev, ide_bar, reg_status);

     assert_bit_set(data, DRDY);
     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 
     assert_bit_set(data, DRDY);
     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 


@@ -499,68 +530,122 @@ static void test_identify(void)
     assert_bit_set(buf[85], 0x20);
 
     ide_test_quit();
     assert_bit_set(buf[85], 0x20);
 
     ide_test_quit();

+    free_pci_device(dev);
+}
+
+/*
+ * Write sector 1 with random data to make IDE storage dirty
+ * Needed for flush tests so that flushes actually go though the block layer
+ */
+static void make_dirty(uint8_t device)
+{
+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;
+    uint8_t status;
+    size_t len = 512;
+    uintptr_t guest_buf;
+    void* buf;
+
+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+
+    guest_buf = guest_alloc(guest_malloc, len);
+    buf = g_malloc(len);
+    memset(buf, rand() % 255 + 1, len);
+    g_assert(guest_buf);
+    g_assert(buf);
+
+    memwrite(guest_buf, buf, len);
+
+    PrdtEntry prdt[] = {
+        {
+            .addr = cpu_to_le32(guest_buf),
+            .size = cpu_to_le32(len | PRDT_EOT),
+        },
+    };
+
+    status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt,
+                              ARRAY_SIZE(prdt), NULL);
+    g_assert_cmphex(status, ==, BM_STS_INTR);
+    assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
+
+    g_free(buf);
+    free_pci_device(dev);

 }
 
 static void test_flush(void)
 {
 }
 
 static void test_flush(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t data;
 
     ide_test_start(
         "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw",
         tmp_path);
 
     uint8_t data;
 
     ide_test_start(
         "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw",
         tmp_path);
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+
+    qtest_irq_intercept_in(global_qtest, "ioapic");
+
+    /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
+    make_dirty(0);
+

     /* Delay the completion of the flush request until we explicitly do it */
     /* Delay the completion of the flush request until we explicitly do it */

-    qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {"
-                         " 'command-line':"
-                         " 'qemu-io ide0-hd0 \"break flush_to_os A\"'} }");
+    g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\""));

 
     /* FLUSH CACHE command on device 0*/
 
     /* FLUSH CACHE command on device 0*/

-    outb(IDE_BASE + reg_device, 0);
-    outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
+    qpci_io_writeb(dev, ide_bar, reg_device, 0);
+    qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);

 
     /* Check status while request is in flight*/
 
     /* Check status while request is in flight*/

-    data = inb(IDE_BASE + reg_status);
+    data = qpci_io_readb(dev, ide_bar, reg_status);

     assert_bit_set(data, BSY | DRDY);
     assert_bit_clear(data, DF | ERR | DRQ);
 
     /* Complete the command */
     assert_bit_set(data, BSY | DRDY);
     assert_bit_clear(data, DF | ERR | DRQ);
 
     /* Complete the command */

-    qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {"
-                         " 'command-line':"
-                         " 'qemu-io ide0-hd0 \"resume A\"'} }");
+    g_free(hmp("qemu-io ide0-hd0 \"resume A\""));

 
     /* Check registers */
 
     /* Check registers */

-    data = inb(IDE_BASE + reg_device);
+    data = qpci_io_readb(dev, ide_bar, reg_device);

     g_assert_cmpint(data & DEV, ==, 0);
 
     do {
     g_assert_cmpint(data & DEV, ==, 0);
 
     do {

-        data = inb(IDE_BASE + reg_status);
+        data = qpci_io_readb(dev, ide_bar, reg_status);

     } while (data & BSY);
 
     assert_bit_set(data, DRDY);
     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 
     ide_test_quit();
     } while (data & BSY);
 
     assert_bit_set(data, DRDY);
     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 
     ide_test_quit();

+    free_pci_device(dev);

 }
 
 static void test_retry_flush(const char *machine)
 {
 }
 
 static void test_retry_flush(const char *machine)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t data;
     const char *s;
 
     prepare_blkdebug_script(debug_path, "flush_to_disk");
 
     ide_test_start(
     uint8_t data;
     const char *s;
 
     prepare_blkdebug_script(debug_path, "flush_to_disk");
 
     ide_test_start(

-        "-vnc none "

         "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw,"
         "rerror=stop,werror=stop",
         debug_path, tmp_path);
 
         "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw,"
         "rerror=stop,werror=stop",
         debug_path, tmp_path);
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+
+    qtest_irq_intercept_in(global_qtest, "ioapic");
+
+    /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
+    make_dirty(0);
+

     /* FLUSH CACHE command on device 0*/
     /* FLUSH CACHE command on device 0*/

-    outb(IDE_BASE + reg_device, 0);
-    outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
+    qpci_io_writeb(dev, ide_bar, reg_device, 0);
+    qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);

 
     /* Check status while request is in flight*/
 
     /* Check status while request is in flight*/

-    data = inb(IDE_BASE + reg_status);
+    data = qpci_io_readb(dev, ide_bar, reg_status);

     assert_bit_set(data, BSY | DRDY);
     assert_bit_clear(data, DF | ERR | DRQ);
 
     assert_bit_set(data, BSY | DRDY);
     assert_bit_clear(data, DF | ERR | DRQ);
 


@@ -571,38 +656,45 @@ static void test_retry_flush(const char *machine)
     qmp_discard_response(s);
 
     /* Check registers */
     qmp_discard_response(s);
 
     /* Check registers */

-    data = inb(IDE_BASE + reg_device);
+    data = qpci_io_readb(dev, ide_bar, reg_device);

     g_assert_cmpint(data & DEV, ==, 0);
 
     do {
     g_assert_cmpint(data & DEV, ==, 0);
 
     do {

-        data = inb(IDE_BASE + reg_status);
+        data = qpci_io_readb(dev, ide_bar, reg_status);

     } while (data & BSY);
 
     assert_bit_set(data, DRDY);
     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 
     ide_test_quit();
     } while (data & BSY);
 
     assert_bit_set(data, DRDY);
     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 
     ide_test_quit();

+    free_pci_device(dev);

 }
 
 static void test_flush_nodev(void)
 {
 }
 
 static void test_flush_nodev(void)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;
+

     ide_test_start("");
 
     ide_test_start("");
 

+    dev = get_pci_device(&bmdma_bar, &ide_bar);
+

     /* FLUSH CACHE command on device 0*/
     /* FLUSH CACHE command on device 0*/

-    outb(IDE_BASE + reg_device, 0);
-    outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
+    qpci_io_writeb(dev, ide_bar, reg_device, 0);
+    qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);

 
     /* Just testing that qemu doesn't crash... */
 
 
     /* Just testing that qemu doesn't crash... */
 

+    free_pci_device(dev);

     ide_test_quit();
 }
 
     ide_test_quit();
 }
 

-static void test_pci_retry_flush(const char *machine)
+static void test_pci_retry_flush(void)

 {
     test_retry_flush("pc");
 }
 
 {
     test_retry_flush("pc");
 }
 

-static void test_isa_retry_flush(const char *machine)
+static void test_isa_retry_flush(void)

 {
     test_retry_flush("isapc");
 }
 {
     test_retry_flush("isapc");
 }


@@ -617,7 +709,8 @@ typedef struct Read10CDB {
     uint16_t padding;
 } __attribute__((__packed__)) Read10CDB;
 
     uint16_t padding;
 } __attribute__((__packed__)) Read10CDB;
 

-static void send_scsi_cdb_read10(uint64_t lba, int nblocks)
+static void send_scsi_cdb_read10(QPCIDevice *dev, QPCIBar ide_bar,
+                                 uint64_t lba, int nblocks)

 {
     Read10CDB pkt = { .padding = 0 };
     int i;
 {
     Read10CDB pkt = { .padding = 0 };
     int i;


@@ -633,7 +726,8 @@ static void send_scsi_cdb_read10(uint64_t lba, int nblocks)
 
     /* Send Packet */
     for (i = 0; i < sizeof(Read10CDB)/2; i++) {
 
     /* Send Packet */
     for (i = 0; i < sizeof(Read10CDB)/2; i++) {

-        outw(IDE_BASE + reg_data, ((uint16_t *)&pkt)[i]);
+        qpci_io_writew(dev, ide_bar, reg_data,
+                       le16_to_cpu(((uint16_t *)&pkt)[i]));

     }
 }
 
     }
 }
 


@@ -646,15 +740,24 @@ static void nsleep(int64_t nsecs)
 
 static uint8_t ide_wait_clear(uint8_t flag)
 {
 
 static uint8_t ide_wait_clear(uint8_t flag)
 {

-    int i;
+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     uint8_t data;
     uint8_t data;

+    time_t st;
+
+    dev = get_pci_device(&bmdma_bar, &ide_bar);

 
     /* Wait with a 5 second timeout */
 
     /* Wait with a 5 second timeout */

-    for (i = 0; i <= 12500000; i++) {
-        data = inb(IDE_BASE + reg_status);
+    time(&st);
+    while (true) {
+        data = qpci_io_readb(dev, ide_bar, reg_status);

         if (!(data & flag)) {
         if (!(data & flag)) {

+            free_pci_device(dev);

             return data;
         }
             return data;
         }

+        if (difftime(time(NULL), st) > 5.0) {
+            break;
+        }

         nsleep(400);
     }
     g_assert_not_reached();
         nsleep(400);
     }
     g_assert_not_reached();


@@ -662,14 +765,18 @@ static uint8_t ide_wait_clear(uint8_t flag)
 
 static void ide_wait_intr(int irq)
 {
 
 static void ide_wait_intr(int irq)
 {

-    int i;
+    time_t st;

     bool intr;
 
     bool intr;
 

-    for (i = 0; i <= 12500000; i++) {
+    time(&st);
+    while (true) {

         intr = get_irq(irq);
         if (intr) {
             return;
         }
         intr = get_irq(irq);
         if (intr) {
             return;
         }

+        if (difftime(time(NULL), st) > 5.0) {
+            break;
+        }

         nsleep(400);
     }
 
         nsleep(400);
     }
 


@@ -678,6 +785,8 @@ static void ide_wait_intr(int irq)
 
 static void cdrom_pio_impl(int nblocks)
 {
 
 static void cdrom_pio_impl(int nblocks)
 {

+    QPCIDevice *dev;
+    QPCIBar bmdma_bar, ide_bar;

     FILE *fh;
     int patt_blocks = MAX(16, nblocks);
     size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks;
     FILE *fh;
     int patt_blocks = MAX(16, nblocks);
     size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks;


@@ -687,39 +796,34 @@ static void cdrom_pio_impl(int nblocks)
     int i, j;
     uint8_t data;
     uint16_t limit;
     int i, j;
     uint8_t data;
     uint16_t limit;

+    size_t ret;

 
     /* Prepopulate the CDROM with an interesting pattern */
     generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE);
     fh = fopen(tmp_path, "w+");
 
     /* Prepopulate the CDROM with an interesting pattern */
     generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE);
     fh = fopen(tmp_path, "w+");

-    fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh);
+    ret = fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh);
+    g_assert_cmpint(ret, ==, patt_blocks);

     fclose(fh);
 
     ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
                    "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
     fclose(fh);
 
     ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
                    "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);

+    dev = get_pci_device(&bmdma_bar, &ide_bar);

     qtest_irq_intercept_in(global_qtest, "ioapic");
 
     /* PACKET command on device 0 */
     qtest_irq_intercept_in(global_qtest, "ioapic");
 
     /* PACKET command on device 0 */

-    outb(IDE_BASE + reg_device, 0);
-    outb(IDE_BASE + reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF);
-    outb(IDE_BASE + reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF));
-    outb(IDE_BASE + reg_command, CMD_PACKET);
-    /* HPD0: Check_Status_A State */
+    qpci_io_writeb(dev, ide_bar, reg_device, 0);
+    qpci_io_writeb(dev, ide_bar, reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF);
+    qpci_io_writeb(dev, ide_bar, reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF));
+    qpci_io_writeb(dev, ide_bar, reg_command, CMD_PACKET);
+    /* HP0: Check_Status_A State */

     nsleep(400);
     data = ide_wait_clear(BSY);
     nsleep(400);
     data = ide_wait_clear(BSY);

-    /* HPD1: Send_Packet State */
+    /* HP1: Send_Packet State */

     assert_bit_set(data, DRQ | DRDY);
     assert_bit_clear(data, ERR | DF | BSY);
 
     /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */
     assert_bit_set(data, DRQ | DRDY);
     assert_bit_clear(data, ERR | DF | BSY);
 
     /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */

-    send_scsi_cdb_read10(0, nblocks);
-
-    /* HPD3: INTRQ_Wait */
-    ide_wait_intr(IDE_PRIMARY_IRQ);
-
-    /* HPD2: Check_Status_B */
-    data = ide_wait_clear(BSY);
-    assert_bit_set(data, DRQ | DRDY);
-    assert_bit_clear(data, ERR | DF | BSY);
+    send_scsi_cdb_read10(dev, ide_bar, 0, nblocks);

 
     /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
      * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.
 
     /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
      * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.


@@ -732,11 +836,26 @@ static void cdrom_pio_impl(int nblocks)
     for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) {
         size_t offset = i * (limit / 2);
         size_t rem = (rxsize / 2) - offset;
     for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) {
         size_t offset = i * (limit / 2);
         size_t rem = (rxsize / 2) - offset;

+
+        /* HP3: INTRQ_Wait */
+        ide_wait_intr(IDE_PRIMARY_IRQ);
+
+        /* HP2: Check_Status_B (and clear IRQ) */
+        data = ide_wait_clear(BSY);
+        assert_bit_set(data, DRQ | DRDY);
+        assert_bit_clear(data, ERR | DF | BSY);
+
+        /* HP4: Transfer_Data */

         for (j = 0; j < MIN((limit / 2), rem); j++) {
         for (j = 0; j < MIN((limit / 2), rem); j++) {

-            rx[offset + j] = inw(IDE_BASE + reg_data);
+            rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, ide_bar,
+                                                       reg_data));

         }
         }

-        ide_wait_intr(IDE_PRIMARY_IRQ);

     }
     }

+
+    /* Check for final completion IRQ */
+    ide_wait_intr(IDE_PRIMARY_IRQ);
+
+    /* Sanity check final state */

     data = ide_wait_clear(DRQ);
     assert_bit_set(data, DRDY);
     assert_bit_clear(data, DRQ | ERR | DF | BSY);
     data = ide_wait_clear(DRQ);
     assert_bit_set(data, DRDY);
     assert_bit_clear(data, DRQ | ERR | DF | BSY);


@@ -745,6 +864,7 @@ static void cdrom_pio_impl(int nblocks)
     g_free(pattern);
     g_free(rx);
     test_bmdma_teardown();
     g_free(pattern);
     g_free(rx);
     test_bmdma_teardown();

+    free_pci_device(dev);

 }
 
 static void test_cdrom_pio(void)
 }
 
 static void test_cdrom_pio(void)


@@ -762,6 +882,7 @@ static void test_cdrom_pio_large(void)
 static void test_cdrom_dma(void)
 {
     static const size_t len = ATAPI_BLOCK_SIZE;
 static void test_cdrom_dma(void)
 {
     static const size_t len = ATAPI_BLOCK_SIZE;

+    size_t ret;

     char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16);
     char *rx = g_malloc0(len);
     uintptr_t guest_buf;
     char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16);
     char *rx = g_malloc0(len);
     uintptr_t guest_buf;


@@ -778,7 +899,8 @@ static void test_cdrom_dma(void)
 
     generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE);
     fh = fopen(tmp_path, "w+");
 
     generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE);
     fh = fopen(tmp_path, "w+");

-    fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh);
+    ret = fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh);
+    g_assert_cmpint(ret, ==, 16);

     fclose(fh);
 
     send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10);
     fclose(fh);
 
     send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10);