log: do not unnecessarily include qom/cpu.h

[qemu.git] / target-m68k / translate.c

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index d6c478fd28d36b2381c4bce2719d579f8042163a..a402bd847ac90b61bb87fd93a1fd37721aafc05f 100644 (file)
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -18,6 +18,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 

+#include "qemu/osdep.h"

 #include "cpu.h"
 #include "disas/disas.h"
 #include "tcg-op.h"
 #include "cpu.h"
 #include "disas/disas.h"
 #include "tcg-op.h"


@@ -28,6 +29,7 @@
 #include "exec/helper-gen.h"
 
 #include "trace-tcg.h"
 #include "exec/helper-gen.h"
 
 #include "trace-tcg.h"

+#include "exec/log.h"

 
 
 //#define DEBUG_DISPATCH 1
 
 
 //#define DEBUG_DISPATCH 1


@@ -129,7 +131,6 @@ typedef struct DisasContext {
     uint32_t fpcr;
     struct TranslationBlock *tb;
     int singlestep_enabled;
     uint32_t fpcr;
     struct TranslationBlock *tb;
     int singlestep_enabled;

-    int is_mem;

     TCGv_i64 mactmp;
     int done_mac;
 } DisasContext;
     TCGv_i64 mactmp;
     int done_mac;
 } DisasContext;


@@ -179,7 +180,6 @@ static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
 {
     TCGv tmp;
     int index = IS_USER(s);
 {
     TCGv tmp;
     int index = IS_USER(s);

-    s->is_mem = 1;

     tmp = tcg_temp_new_i32();
     switch(opsize) {
     case OS_BYTE:
     tmp = tcg_temp_new_i32();
     switch(opsize) {
     case OS_BYTE:


@@ -209,7 +209,6 @@ static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
 {
     TCGv_i64 tmp;
     int index = IS_USER(s);
 {
     TCGv_i64 tmp;
     int index = IS_USER(s);

-    s->is_mem = 1;

     tmp = tcg_temp_new_i64();
     tcg_gen_qemu_ldf64(tmp, addr, index);
     gen_throws_exception = gen_last_qop;
     tmp = tcg_temp_new_i64();
     tcg_gen_qemu_ldf64(tmp, addr, index);
     gen_throws_exception = gen_last_qop;


@@ -220,7 +219,6 @@ static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
 {
     int index = IS_USER(s);
 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
 {
     int index = IS_USER(s);

-    s->is_mem = 1;

     switch(opsize) {
     case OS_BYTE:
         tcg_gen_qemu_st8(val, addr, index);
     switch(opsize) {
     case OS_BYTE:
         tcg_gen_qemu_st8(val, addr, index);


@@ -241,7 +239,6 @@ static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
 {
     int index = IS_USER(s);
 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
 {
     int index = IS_USER(s);

-    s->is_mem = 1;

     tcg_gen_qemu_stf64(val, addr, index);
     gen_throws_exception = gen_last_qop;
 }
     tcg_gen_qemu_stf64(val, addr, index);
     gen_throws_exception = gen_last_qop;
 }


@@ -297,8 +294,7 @@ static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
 
 /* Handle a base + index + displacement effective addresss.
    A NULL_QREG base means pc-relative.  */
 
 /* Handle a base + index + displacement effective addresss.
    A NULL_QREG base means pc-relative.  */

-static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize,
-                            TCGv base)
+static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)

 {
     uint32_t offset;
     uint16_t ext;
 {
     uint32_t offset;
     uint16_t ext;


@@ -529,7 +525,7 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
         return tmp;
     case 6: /* Indirect index + displacement.  */
         reg = AREG(insn, 0);
         return tmp;
     case 6: /* Indirect index + displacement.  */
         reg = AREG(insn, 0);

-        return gen_lea_indexed(env, s, opsize, reg);
+        return gen_lea_indexed(env, s, reg);

     case 7: /* Other */
         switch (insn & 7) {
         case 0: /* Absolute short.  */
     case 7: /* Other */
         switch (insn & 7) {
         case 0: /* Absolute short.  */


@@ -545,7 +541,7 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
             s->pc += 2;
             return tcg_const_i32(offset);
         case 3: /* pc index+displacement.  */
             s->pc += 2;
             return tcg_const_i32(offset);
         case 3: /* pc index+displacement.  */

-            return gen_lea_indexed(env, s, opsize, NULL_QREG);
+            return gen_lea_indexed(env, s, NULL_QREG);

         case 4: /* Immediate.  */
         default:
             return NULL_QREG;
         case 4: /* Immediate.  */
         default:
             return NULL_QREG;


@@ -2227,7 +2223,6 @@ DISAS_INSN(fpu)
             mask = 0x80;
             for (i = 0; i < 8; i++) {
                 if (ext & mask) {
             mask = 0x80;
             for (i = 0; i < 8; i++) {
                 if (ext & mask) {

-                    s->is_mem = 1;

                     dest = FREG(i, 0);
                     if (ext & (1 << 13)) {
                         /* store */
                     dest = FREG(i, 0);
                     if (ext & (1 << 13)) {
                         /* store */


@@ -2687,7 +2682,7 @@ DISAS_INSN(from_mac)
     if (s->env->macsr & MACSR_FI) {
         gen_helper_get_macf(rx, cpu_env, acc);
     } else if ((s->env->macsr & MACSR_OMC) == 0) {
     if (s->env->macsr & MACSR_FI) {
         gen_helper_get_macf(rx, cpu_env, acc);
     } else if ((s->env->macsr & MACSR_OMC) == 0) {

-        tcg_gen_trunc_i64_i32(rx, acc);
+        tcg_gen_extrl_i64_i32(rx, acc);

     } else if (s->env->macsr & MACSR_SU) {
         gen_helper_get_macs(rx, acc);
     } else {
     } else if (s->env->macsr & MACSR_SU) {
         gen_helper_get_macs(rx, acc);
     } else {


@@ -2962,10 +2957,6 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
 {
     uint16_t insn;
 
 {
     uint16_t insn;
 

-    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(s->pc);
-    }
-

     insn = cpu_lduw_code(env, s->pc);
     s->pc += 2;
 
     insn = cpu_lduw_code(env, s->pc);
     s->pc += 2;
 


@@ -2973,15 +2964,11 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
 }
 
 /* generate intermediate code for basic block 'tb'.  */
 }
 
 /* generate intermediate code for basic block 'tb'.  */

-static inline void
-gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
-                               bool search_pc)
+void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)

 {
 {

+    M68kCPU *cpu = m68k_env_get_cpu(env);

     CPUState *cs = CPU(cpu);
     CPUState *cs = CPU(cpu);

-    CPUM68KState *env = &cpu->env;

     DisasContext dc1, *dc = &dc1;
     DisasContext dc1, *dc = &dc1;

-    CPUBreakpoint *bp;
-    int j, lj;

     target_ulong pc_start;
     int pc_offset;
     int num_insns;
     target_ulong pc_start;
     int pc_offset;
     int num_insns;


@@ -2999,45 +2986,40 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
     dc->singlestep_enabled = cs->singlestep_enabled;
     dc->fpcr = env->fpcr;
     dc->user = (env->sr & SR_S) == 0;
     dc->singlestep_enabled = cs->singlestep_enabled;
     dc->fpcr = env->fpcr;
     dc->user = (env->sr & SR_S) == 0;

-    dc->is_mem = 0;

     dc->done_mac = 0;
     dc->done_mac = 0;

-    lj = -1;

     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;

-    if (max_insns == 0)
+    if (max_insns == 0) {

         max_insns = CF_COUNT_MASK;
         max_insns = CF_COUNT_MASK;

+    }
+    if (max_insns > TCG_MAX_INSNS) {
+        max_insns = TCG_MAX_INSNS;
+    }

 
     gen_tb_start(tb);
     do {
         pc_offset = dc->pc - pc_start;
         gen_throws_exception = NULL;
 
     gen_tb_start(tb);
     do {
         pc_offset = dc->pc - pc_start;
         gen_throws_exception = NULL;

-        if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
-            QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
-                if (bp->pc == dc->pc) {
-                    gen_exception(dc, dc->pc, EXCP_DEBUG);
-                    dc->is_jmp = DISAS_JUMP;
-                    break;
-                }
-            }
-            if (dc->is_jmp)
-                break;
-        }
-        if (search_pc) {
-            j = tcg_op_buf_count();
-            if (lj < j) {
-                lj++;
-                while (lj < j)
-                    tcg_ctx.gen_opc_instr_start[lj++] = 0;
-            }
-            tcg_ctx.gen_opc_pc[lj] = dc->pc;
-            tcg_ctx.gen_opc_instr_start[lj] = 1;
-            tcg_ctx.gen_opc_icount[lj] = num_insns;
+        tcg_gen_insn_start(dc->pc);
+        num_insns++;
+
+        if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+            gen_exception(dc, dc->pc, EXCP_DEBUG);
+            dc->is_jmp = DISAS_JUMP;
+            /* The address covered by the breakpoint must be included in
+               [tb->pc, tb->pc + tb->size) in order to for it to be
+               properly cleared -- thus we increment the PC here so that
+               the logic setting tb->size below does the right thing.  */
+            dc->pc += 2;
+            break;

         }
         }

-        if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
+
+        if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {

             gen_io_start();
             gen_io_start();

+        }
+

         dc->insn_pc = dc->pc;
        disas_m68k_insn(env, dc);
         dc->insn_pc = dc->pc;
        disas_m68k_insn(env, dc);

-        num_insns++;

     } while (!dc->is_jmp && !tcg_op_buf_full() &&
              !cs->singlestep_enabled &&
              !singlestep &&
     } while (!dc->is_jmp && !tcg_op_buf_full() &&
              !cs->singlestep_enabled &&
              !singlestep &&


@@ -3081,28 +3063,8 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
         qemu_log("\n");
     }
 #endif
         qemu_log("\n");
     }
 #endif

-    if (search_pc) {
-        j = tcg_op_buf_count();
-        lj++;
-        while (lj <= j)
-            tcg_ctx.gen_opc_instr_start[lj++] = 0;
-    } else {
-        tb->size = dc->pc - pc_start;
-        tb->icount = num_insns;
-    }
-
-    //optimize_flags();
-    //expand_target_qops();
-}
-
-void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, false);
-}
-
-void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, true);
+    tb->size = dc->pc - pc_start;
+    tb->icount = num_insns;

 }
 
 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
 }
 
 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,


@@ -3128,7 +3090,8 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
     cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
 }
 
     cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
 }
 

-void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
+                          target_ulong *data)

 {
 {

-    env->pc = tcg_ctx.gen_opc_pc[pc_pos];
+    env->pc = data[0];

 }
 }