target/ppc: Add SPR TBU40

[qemu.git] / hw / riscv / sifive_uart.c

diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 215990b443e6b21f9bd98ba368fe3dde2ade5b86..a403ae90f53bcc8e736ab6e62e2767f602cd1448 100644 (file)
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -22,7 +22,6 @@
 #include "hw/sysbus.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
-#include "target/riscv/cpu.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
 #include "hw/riscv/sifive_uart.h"