* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "exec.h"
+#include "host-utils.h"
+#include "helper.h"
#include "helper_regs.h"
#include "op_helper.h"
#define MEMSUFFIX _kernel
#include "op_helper.h"
#include "op_helper_mem.h"
-#if defined(TARGET_PPC64H)
#define MEMSUFFIX _hypv
#include "op_helper.h"
#include "op_helper_mem.h"
#endif
-#endif
//#define DEBUG_OP
//#define DEBUG_EXCEPTIONS
/*****************************************************************************/
/* Exceptions processing helpers */
-void do_raise_exception_err (uint32_t exception, int error_code)
-{
-#if 0
- printf("Raise exception %3x code : %d\n", exception, error_code);
-#endif
- env->exception_index = exception;
- env->error_code = error_code;
- cpu_loop_exit();
-}
-
-void do_raise_exception (uint32_t exception)
+void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
{
- do_raise_exception_err(exception, 0);
+ raise_exception_err(env, exception, error_code);
}
-void cpu_dump_EA (target_ulong EA);
-void do_print_mem_EA (target_ulong EA)
+void helper_raise_debug (void)
{
- cpu_dump_EA(EA);
+ raise_exception(env, EXCP_DEBUG);
}
/*****************************************************************************/
/* Registers load and stores */
-void do_load_cr (void)
+target_ulong helper_load_cr (void)
{
- T0 = (env->crf[0] << 28) |
- (env->crf[1] << 24) |
- (env->crf[2] << 20) |
- (env->crf[3] << 16) |
- (env->crf[4] << 12) |
- (env->crf[5] << 8) |
- (env->crf[6] << 4) |
- (env->crf[7] << 0);
+ return (env->crf[0] << 28) |
+ (env->crf[1] << 24) |
+ (env->crf[2] << 20) |
+ (env->crf[3] << 16) |
+ (env->crf[4] << 12) |
+ (env->crf[5] << 8) |
+ (env->crf[6] << 4) |
+ (env->crf[7] << 0);
}
-void do_store_cr (uint32_t mask)
+void helper_store_cr (target_ulong val, uint32_t mask)
{
int i, sh;
for (i = 0, sh = 7; i < 8; i++, sh--) {
if (mask & (1 << sh))
- env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
+ env->crf[i] = (val >> (sh * 4)) & 0xFUL;
}
}
}
/*****************************************************************************/
-/* Fixed point operations helpers */
-void do_adde (void)
-{
- T2 = T0;
- T0 += T1 + xer_ca;
- if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
- (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
-}
+/* Memory load and stores */
-#if defined(TARGET_PPC64)
-void do_adde_64 (void)
+static always_inline target_ulong get_addr(target_ulong addr)
{
- T2 = T0;
- T0 += T1 + xer_ca;
- if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
- (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
-}
-#endif
-
-void do_addmeo (void)
-{
- T1 = T0;
- T0 += xer_ca + (-1);
- if (likely(!((uint32_t)T1 &
- ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely(T1 != 0))
- xer_ca = 1;
-}
-
#if defined(TARGET_PPC64)
-void do_addmeo_64 (void)
-{
- T1 = T0;
- T0 += xer_ca + (-1);
- if (likely(!((uint64_t)T1 &
- ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely(T1 != 0))
- xer_ca = 1;
-}
+ if (msr_sf)
+ return addr;
+ else
#endif
-
-void do_divwo (void)
-{
- if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
- (int32_t)T1 == 0))) {
- xer_ov = 0;
- T0 = (int32_t)T0 / (int32_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = (-1) * ((uint32_t)T0 >> 31);
- }
+ return (uint32_t)addr;
}
-#if defined(TARGET_PPC64)
-void do_divdo (void)
+void helper_lmw (target_ulong addr, uint32_t reg)
{
- if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
- (int64_t)T1 == 0))) {
- xer_ov = 0;
- T0 = (int64_t)T0 / (int64_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = (-1ULL) * ((uint64_t)T0 >> 63);
+#ifdef CONFIG_USER_ONLY
+#define ldfun ldl_raw
+#else
+ int (*ldfun)(target_ulong);
+
+ switch (env->mmu_idx) {
+ default:
+ case 0: ldfun = ldl_user;
+ break;
+ case 1: ldfun = ldl_kernel;
+ break;
+ case 2: ldfun = ldl_hypv;
+ break;
}
-}
#endif
-
-void do_divwuo (void)
-{
- if (likely((uint32_t)T1 != 0)) {
- xer_ov = 0;
- T0 = (uint32_t)T0 / (uint32_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = 0;
+ for (; reg < 32; reg++, addr += 4) {
+ if (msr_le)
+ env->gpr[reg] = bswap32(ldfun(get_addr(addr)));
+ else
+ env->gpr[reg] = ldfun(get_addr(addr));
}
}
-#if defined(TARGET_PPC64)
-void do_divduo (void)
+void helper_stmw (target_ulong addr, uint32_t reg)
{
- if (likely((uint64_t)T1 != 0)) {
- xer_ov = 0;
- T0 = (uint64_t)T0 / (uint64_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = 0;
+#ifdef CONFIG_USER_ONLY
+#define stfun stl_raw
+#else
+ void (*stfun)(target_ulong, int);
+
+ switch (env->mmu_idx) {
+ default:
+ case 0: stfun = stl_user;
+ break;
+ case 1: stfun = stl_kernel;
+ break;
+ case 2: stfun = stl_hypv;
+ break;
}
-}
#endif
-
-void do_mullwo (void)
-{
- int64_t res = (int64_t)T0 * (int64_t)T1;
-
- if (likely((int32_t)res == res)) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
+ for (; reg < 32; reg++, addr += 4) {
+ if (msr_le)
+ stfun(get_addr(addr), bswap32((uint32_t)env->gpr[reg]));
+ else
+ stfun(get_addr(addr), (uint32_t)env->gpr[reg]);
}
- T0 = (int32_t)res;
}
-#if defined(TARGET_PPC64)
-void do_mulldo (void)
+static void do_dcbz(target_ulong addr, int dcache_line_size)
{
- int64_t th;
- uint64_t tl;
+ target_long mask = get_addr(~(dcache_line_size - 1));
+ int i;
+#ifdef CONFIG_USER_ONLY
+#define stfun stl_raw
+#else
+ void (*stfun)(target_ulong, int);
- muls64(&tl, &th, T0, T1);
- /* If th != 0 && th != -1, then we had an overflow */
- if (likely((th + 1) <= 1)) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
+ switch (env->mmu_idx) {
+ default:
+ case 0: stfun = stl_user;
+ break;
+ case 1: stfun = stl_kernel;
+ break;
+ case 2: stfun = stl_hypv;
+ break;
}
- T0 = (int64_t)tl;
-}
#endif
-
-void do_nego (void)
-{
- if (likely((int32_t)T0 != INT32_MIN)) {
- xer_ov = 0;
- T0 = -(int32_t)T0;
- } else {
- xer_ov = 1;
- xer_so = 1;
+ addr &= mask;
+ for (i = 0 ; i < dcache_line_size ; i += 4) {
+ stfun(addr + i , 0);
}
+ if ((env->reserve & mask) == addr)
+ env->reserve = (target_ulong)-1ULL;
}
-#if defined(TARGET_PPC64)
-void do_nego_64 (void)
+void helper_dcbz(target_ulong addr)
{
- if (likely((int64_t)T0 != INT64_MIN)) {
- xer_ov = 0;
- T0 = -(int64_t)T0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
+ do_dcbz(addr, env->dcache_line_size);
}
-#endif
-void do_subfe (void)
+void helper_dcbz_970(target_ulong addr)
{
- T0 = T1 + ~T0 + xer_ca;
- if (likely((uint32_t)T0 >= (uint32_t)T1 &&
- (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
+ do_dcbz(addr, 32);
+ else
+ do_dcbz(addr, env->dcache_line_size);
}
+/*****************************************************************************/
+/* Fixed point operations helpers */
#if defined(TARGET_PPC64)
-void do_subfe_64 (void)
+
+/* multiply high word */
+uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
{
- T0 = T1 + ~T0 + xer_ca;
- if (likely((uint64_t)T0 >= (uint64_t)T1 &&
- (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ uint64_t tl, th;
+
+ muls64(&tl, &th, arg1, arg2);
+ return th;
}
-#endif
-void do_subfmeo (void)
+/* multiply high word unsigned */
+uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
{
- T1 = T0;
- T0 = ~T0 + xer_ca - 1;
- if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
- (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely((uint32_t)T1 != UINT32_MAX))
- xer_ca = 1;
+ uint64_t tl, th;
+
+ mulu64(&tl, &th, arg1, arg2);
+ return th;
}
-#if defined(TARGET_PPC64)
-void do_subfmeo_64 (void)
+uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
{
- T1 = T0;
- T0 = ~T0 + xer_ca - 1;
- if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
- (1ULL << 63)))) {
- xer_ov = 0;
+ int64_t th;
+ uint64_t tl;
+
+ muls64(&tl, (uint64_t *)&th, arg1, arg2);
+ /* If th != 0 && th != -1, then we had an overflow */
+ if (likely((uint64_t)(th + 1) <= 1)) {
+ env->xer &= ~(1 << XER_OV);
} else {
- xer_ov = 1;
- xer_so = 1;
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
}
- if (likely((uint64_t)T1 != UINT64_MAX))
- xer_ca = 1;
+ return (int64_t)tl;
}
#endif
-void do_subfzeo (void)
+target_ulong helper_cntlzw (target_ulong t)
{
- T1 = T0;
- T0 = ~T0 + xer_ca;
- if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
- ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ return clz32(t);
}
#if defined(TARGET_PPC64)
-void do_subfzeo_64 (void)
+target_ulong helper_cntlzd (target_ulong t)
{
- T1 = T0;
- T0 = ~T0 + xer_ca;
- if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
- ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ return clz64(t);
}
#endif
/* shift right arithmetic helper */
-void do_sraw (void)
+target_ulong helper_sraw (target_ulong value, target_ulong shift)
{
int32_t ret;
- if (likely(!(T1 & 0x20UL))) {
- if (likely((uint32_t)T1 != 0)) {
- ret = (int32_t)T0 >> (T1 & 0x1fUL);
- if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
- xer_ca = 0;
+ if (likely(!(shift & 0x20))) {
+ if (likely((uint32_t)shift != 0)) {
+ shift &= 0x1f;
+ ret = (int32_t)value >> shift;
+ if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
+ env->xer &= ~(1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer |= (1 << XER_CA);
}
} else {
- ret = T0;
- xer_ca = 0;
+ ret = (int32_t)value;
+ env->xer &= ~(1 << XER_CA);
}
} else {
- ret = (-1) * ((uint32_t)T0 >> 31);
- if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
- xer_ca = 0;
+ ret = (int32_t)value >> 31;
+ if (ret) {
+ env->xer |= (1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer &= ~(1 << XER_CA);
}
}
- T0 = ret;
+ return (target_long)ret;
}
#if defined(TARGET_PPC64)
-void do_srad (void)
+target_ulong helper_srad (target_ulong value, target_ulong shift)
{
int64_t ret;
- if (likely(!(T1 & 0x40UL))) {
- if (likely((uint64_t)T1 != 0)) {
- ret = (int64_t)T0 >> (T1 & 0x3FUL);
- if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
- xer_ca = 0;
+ if (likely(!(shift & 0x40))) {
+ if (likely((uint64_t)shift != 0)) {
+ shift &= 0x3f;
+ ret = (int64_t)value >> shift;
+ if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
+ env->xer &= ~(1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer |= (1 << XER_CA);
}
} else {
- ret = T0;
- xer_ca = 0;
+ ret = (int64_t)value;
+ env->xer &= ~(1 << XER_CA);
}
} else {
- ret = (-1) * ((uint64_t)T0 >> 63);
- if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
- xer_ca = 0;
+ ret = (int64_t)value >> 63;
+ if (ret) {
+ env->xer |= (1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer &= ~(1 << XER_CA);
}
}
- T0 = ret;
+ return ret;
}
#endif
-static always_inline int popcnt (uint32_t val)
+target_ulong helper_popcntb (target_ulong val)
{
- int i;
+ val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
+ val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
+ val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
+ return val;
+}
- for (i = 0; val != 0;)
- val = val ^ (val - 1);
+#if defined(TARGET_PPC64)
+target_ulong helper_popcntb_64 (target_ulong val)
+{
+ val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
+ val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
+ val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
+ return val;
+}
+#endif
- return i;
+/*****************************************************************************/
+/* Floating point operations helpers */
+uint64_t helper_float32_to_float64(uint32_t arg)
+{
+ CPU_FloatU f;
+ CPU_DoubleU d;
+ f.l = arg;
+ d.d = float32_to_float64(f.f, &env->fp_status);
+ return d.ll;
}
-void do_popcntb (void)
+uint32_t helper_float64_to_float32(uint64_t arg)
{
- uint32_t ret;
- int i;
+ CPU_FloatU f;
+ CPU_DoubleU d;
+ d.ll = arg;
+ f.f = float64_to_float32(d.d, &env->fp_status);
+ return f.l;
+}
- ret = 0;
- for (i = 0; i < 32; i += 8)
- ret |= popcnt((T0 >> i) & 0xFF) << i;
- T0 = ret;
+static always_inline int fpisneg (float64 d)
+{
+ CPU_DoubleU u;
+
+ u.d = d;
+
+ return u.ll >> 63 != 0;
}
-#if defined(TARGET_PPC64)
-void do_popcntb_64 (void)
+static always_inline int isden (float64 d)
{
- uint64_t ret;
- int i;
+ CPU_DoubleU u;
- ret = 0;
- for (i = 0; i < 64; i += 8)
- ret |= popcnt((T0 >> i) & 0xFF) << i;
- T0 = ret;
+ u.d = d;
+
+ return ((u.ll >> 52) & 0x7FF) == 0;
}
-#endif
-/*****************************************************************************/
-/* Floating point operations helpers */
-static always_inline int fpisneg (float64 f)
+static always_inline int iszero (float64 d)
{
- union {
- float64 f;
- uint64_t u;
- } u;
+ CPU_DoubleU u;
- u.f = f;
+ u.d = d;
- return u.u >> 63 != 0;
+ return (u.ll & ~0x8000000000000000ULL) == 0;
}
-static always_inline int isden (float f)
+static always_inline int isinfinity (float64 d)
{
- union {
- float64 f;
- uint64_t u;
- } u;
+ CPU_DoubleU u;
- u.f = f;
+ u.d = d;
- return ((u.u >> 52) & 0x7FF) == 0;
+ return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
+ (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
}
-static always_inline int iszero (float64 f)
+#ifdef CONFIG_SOFTFLOAT
+static always_inline int isfinite (float64 d)
{
- union {
- float64 f;
- uint64_t u;
- } u;
+ CPU_DoubleU u;
- u.f = f;
+ u.d = d;
- return (u.u & ~0x8000000000000000ULL) == 0;
+ return (((u.ll >> 52) & 0x7FF) != 0x7FF);
}
-static always_inline int isinfinity (float64 f)
+static always_inline int isnormal (float64 d)
{
- union {
- float64 f;
- uint64_t u;
- } u;
+ CPU_DoubleU u;
- u.f = f;
+ u.d = d;
- return ((u.u >> 52) & 0x3FF) == 0x3FF &&
- (u.u & 0x000FFFFFFFFFFFFFULL) == 0;
+ uint32_t exp = (u.ll >> 52) & 0x7FF;
+ return ((0 < exp) && (exp < 0x7FF));
}
+#endif
-void do_compute_fprf (int set_fprf)
+uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
{
+ CPU_DoubleU farg;
int isneg;
-
- isneg = fpisneg(FT0);
- if (unlikely(float64_is_nan(FT0))) {
- if (float64_is_signaling_nan(FT0)) {
+ int ret;
+ farg.ll = arg;
+ isneg = fpisneg(farg.d);
+ if (unlikely(float64_is_nan(farg.d))) {
+ if (float64_is_signaling_nan(farg.d)) {
/* Signaling NaN: flags are undefined */
- T0 = 0x00;
+ ret = 0x00;
} else {
/* Quiet NaN */
- T0 = 0x11;
+ ret = 0x11;
}
- } else if (unlikely(isinfinity(FT0))) {
+ } else if (unlikely(isinfinity(farg.d))) {
/* +/- infinity */
if (isneg)
- T0 = 0x09;
+ ret = 0x09;
else
- T0 = 0x05;
+ ret = 0x05;
} else {
- if (iszero(FT0)) {
+ if (iszero(farg.d)) {
/* +/- zero */
if (isneg)
- T0 = 0x12;
+ ret = 0x12;
else
- T0 = 0x02;
+ ret = 0x02;
} else {
- if (isden(FT0)) {
+ if (isden(farg.d)) {
/* Denormalized numbers */
- T0 = 0x10;
+ ret = 0x10;
} else {
/* Normalized numbers */
- T0 = 0x00;
+ ret = 0x00;
}
if (isneg) {
- T0 |= 0x08;
+ ret |= 0x08;
} else {
- T0 |= 0x04;
+ ret |= 0x04;
}
}
}
if (set_fprf) {
/* We update FPSCR_FPRF */
env->fpscr &= ~(0x1F << FPSCR_FPRF);
- env->fpscr |= T0 << FPSCR_FPRF;
+ env->fpscr |= ret << FPSCR_FPRF;
}
/* We just need fpcc to update Rc1 */
- T0 &= 0xF;
+ return ret & 0xF;
}
/* Floating-point invalid operations exception */
-static always_inline void fload_invalid_op_excp (int op)
+static always_inline uint64_t fload_invalid_op_excp (int op)
{
+ uint64_t ret = 0;
int ve;
ve = fpscr_ve;
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
if (ve == 0) {
/* Set the result to quiet NaN */
- FT0 = (uint64_t)-1;
+ ret = UINT64_MAX;
env->fpscr &= ~(0xF << FPSCR_FPCC);
env->fpscr |= 0x11 << FPSCR_FPCC;
}
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
if (ve == 0) {
/* Set the result to quiet NaN */
- FT0 = (uint64_t)-1;
+ ret = UINT64_MAX;
env->fpscr &= ~(0xF << FPSCR_FPCC);
env->fpscr |= 0x11 << FPSCR_FPCC;
}
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
if (msr_fe0 != 0 || msr_fe1 != 0)
- do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
}
+ return ret;
}
-static always_inline void float_zero_divide_excp (void)
+static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
{
- union {
- float64 f;
- uint64_t u;
- } u0, u1;
-
env->fpscr |= 1 << FPSCR_ZX;
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
/* Update the floating-point exception summary */
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
if (msr_fe0 != 0 || msr_fe1 != 0) {
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
}
} else {
/* Set the result to infinity */
- u0.f = FT0;
- u1.f = FT1;
- u0.u = ((u0.u ^ u1.u) & 0x8000000000000000ULL);
- u0.u |= 0x3FFULL << 52;
- FT0 = u0.f;
+ arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
+ arg1 |= 0x7FFULL << 52;
}
+ return arg1;
}
static always_inline void float_overflow_excp (void)
set_float_rounding_mode(rnd_type, &env->fp_status);
}
-void do_fpscr_setbit (int bit)
+void helper_fpscr_setbit (uint32_t bit)
{
int prev;
}
}
-#if defined(WORDS_BIGENDIAN)
-#define WORD0 0
-#define WORD1 1
-#else
-#define WORD0 1
-#define WORD1 0
-#endif
-void do_store_fpscr (uint32_t mask)
+void helper_store_fpscr (uint64_t arg, uint32_t mask)
{
/*
* We use only the 32 LSB of the incoming fpr
*/
- union {
- double d;
- struct {
- uint32_t u[2];
- } s;
- } u;
uint32_t prev, new;
int i;
- u.d = FT0;
prev = env->fpscr;
- new = u.s.u[WORD1];
+ new = (uint32_t)arg;
new &= ~0x90000000;
new |= prev & 0x90000000;
for (i = 0; i < 7; i++) {
/* Update VX and FEX */
if (fpscr_ix != 0)
env->fpscr |= 1 << FPSCR_VX;
+ else
+ env->fpscr &= ~(1 << FPSCR_VX);
if ((fpscr_ex & fpscr_eex) != 0) {
env->fpscr |= 1 << FPSCR_FEX;
env->exception_index = POWERPC_EXCP_PROGRAM;
/* XXX: we should compute it properly */
env->error_code = POWERPC_EXCP_FP;
}
+ else
+ env->fpscr &= ~(1 << FPSCR_FEX);
fpscr_set_rounding_mode();
}
-#undef WORD0
-#undef WORD1
-#ifdef CONFIG_SOFTFLOAT
-void do_float_check_status (void)
+void helper_float_check_status (void)
{
+#ifdef CONFIG_SOFTFLOAT
if (env->exception_index == POWERPC_EXCP_PROGRAM &&
(env->error_code & POWERPC_EXCP_FP)) {
/* Differred floating-point exception after target FPR update */
if (msr_fe0 != 0 || msr_fe1 != 0)
- do_raise_exception_err(env->exception_index, env->error_code);
+ raise_exception_err(env, env->exception_index, env->error_code);
} else if (env->fp_status.float_exception_flags & float_flag_overflow) {
float_overflow_excp();
} else if (env->fp_status.float_exception_flags & float_flag_underflow) {
} else if (env->fp_status.float_exception_flags & float_flag_inexact) {
float_inexact_excp();
}
+#else
+ if (env->exception_index == POWERPC_EXCP_PROGRAM &&
+ (env->error_code & POWERPC_EXCP_FP)) {
+ /* Differred floating-point exception after target FPR update */
+ if (msr_fe0 != 0 || msr_fe1 != 0)
+ raise_exception_err(env, env->exception_index, env->error_code);
+ }
+ RETURN();
+#endif
+}
+
+#ifdef CONFIG_SOFTFLOAT
+void helper_reset_fpstatus (void)
+{
+ env->fp_status.float_exception_flags = 0;
}
#endif
-#if USE_PRECISE_EMULATION
-void do_fadd (void)
+/* fadd - fadd. */
+uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1))) {
+ CPU_DoubleU farg1, farg2;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
/* sNaN addition */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (likely(isfinite(FT0) || isfinite(FT1) ||
- fpisneg(FT0) == fpisneg(FT1))) {
- FT0 = float64_add(FT0, FT1, &env->fp_status);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
+ fpisneg(farg1.d) == fpisneg(farg2.d))) {
+ farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
} else {
/* Magnitude subtraction of infinities */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
+ farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
}
+#else
+ farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
+#endif
+ return farg1.ll;
}
-void do_fsub (void)
+/* fsub - fsub. */
+uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1))) {
+ CPU_DoubleU farg1, farg2;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
+{
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
/* sNaN subtraction */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (likely(isfinite(FT0) || isfinite(FT1) ||
- fpisneg(FT0) != fpisneg(FT1))) {
- FT0 = float64_sub(FT0, FT1, &env->fp_status);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
+ fpisneg(farg1.d) != fpisneg(farg2.d))) {
+ farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
} else {
/* Magnitude subtraction of infinities */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
}
}
+#else
+ farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
+#endif
+ return farg1.ll;
+}
-void do_fmul (void)
+/* fmul - fmul. */
+uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1))) {
+ CPU_DoubleU farg1, farg2;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
/* sNaN multiplication */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
- (iszero(FT0) && isinfinity(FT1)))) {
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
+ (iszero(farg1.d) && isinfinity(farg2.d)))) {
/* Multiplication of zero by infinity */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
} else {
- FT0 = float64_mul(FT0, FT1, &env->fp_status);
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
}
}
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+#endif
+ return farg1.ll;
+}
-void do_fdiv (void)
+/* fdiv - fdiv. */
+uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1))) {
+ CPU_DoubleU farg1, farg2;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
/* sNaN division */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
/* Division of infinity by infinity */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
- } else if (unlikely(iszero(FT1))) {
- if (iszero(FT0)) {
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
+ } else if (unlikely(iszero(farg2.d))) {
+ if (iszero(farg1.d)) {
/* Division of zero by zero */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
+ farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
} else {
/* Division by zero */
- float_zero_divide_excp();
+ farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
}
} else {
- FT0 = float64_div(FT0, FT1, &env->fp_status);
+ farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
}
+#else
+ farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
+#endif
+ return farg1.ll;
}
-#endif /* USE_PRECISE_EMULATION */
-void do_fctiw (void)
+/* fabs */
+uint64_t helper_fabs (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
+ CPU_DoubleU farg;
+
+ farg.ll = arg;
+ farg.d = float64_abs(farg.d);
+ return farg.ll;
+}
+
+/* fnabs */
+uint64_t helper_fnabs (uint64_t arg)
+{
+ CPU_DoubleU farg;
+
+ farg.ll = arg;
+ farg.d = float64_abs(farg.d);
+ farg.d = float64_chs(farg.d);
+ return farg.ll;
+}
+
+/* fneg */
+uint64_t helper_fneg (uint64_t arg)
+{
+ CPU_DoubleU farg;
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ farg.ll = arg;
+ farg.d = float64_chs(farg.d);
+ return farg.ll;
+}
+
+/* fctiw - fctiw. */
+uint64_t helper_fctiw (uint64_t arg)
+{
+ CPU_DoubleU farg;
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
- } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
/* qNan / infinity conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- p.i = float64_to_int32(FT0, &env->fp_status);
+ farg.ll = float64_to_int32(farg.d, &env->fp_status);
#if USE_PRECISE_EMULATION
/* XXX: higher bits are not supposed to be significant.
* to make tests easier, return the same as a real PowerPC 750
*/
- p.i |= 0xFFF80000ULL << 32;
+ farg.ll |= 0xFFF80000ULL << 32;
#endif
- FT0 = p.d;
}
+ return farg.ll;
}
-void do_fctiwz (void)
+/* fctiwz - fctiwz. */
+uint64_t helper_fctiwz (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
- } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
/* qNan / infinity conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
+ farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
#if USE_PRECISE_EMULATION
/* XXX: higher bits are not supposed to be significant.
* to make tests easier, return the same as a real PowerPC 750
*/
- p.i |= 0xFFF80000ULL << 32;
+ farg.ll |= 0xFFF80000ULL << 32;
#endif
- FT0 = p.d;
}
+ return farg.ll;
}
#if defined(TARGET_PPC64)
-void do_fcfid (void)
+/* fcfid - fcfid. */
+uint64_t helper_fcfid (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
-
- p.d = FT0;
- FT0 = int64_to_float64(p.i, &env->fp_status);
+ CPU_DoubleU farg;
+ farg.d = int64_to_float64(arg, &env->fp_status);
+ return farg.ll;
}
-void do_fctid (void)
+/* fctid - fctid. */
+uint64_t helper_fctid (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
- } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
/* qNan / infinity conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- p.i = float64_to_int64(FT0, &env->fp_status);
- FT0 = p.d;
+ farg.ll = float64_to_int64(farg.d, &env->fp_status);
}
+ return farg.ll;
}
-void do_fctidz (void)
+/* fctidz - fctidz. */
+uint64_t helper_fctidz (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
- } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
/* qNan / infinity conversion */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
- FT0 = p.d;
+ farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
}
+ return farg.ll;
}
#endif
-static always_inline void do_fri (int rounding_mode)
+static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
{
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ CPU_DoubleU farg;
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN round */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
- } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
/* qNan / infinity round */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
set_float_rounding_mode(rounding_mode, &env->fp_status);
- FT0 = float64_round_to_int(FT0, &env->fp_status);
+ farg.ll = float64_round_to_int(farg.d, &env->fp_status);
/* Restore rounding mode from FPSCR */
fpscr_set_rounding_mode();
}
+ return farg.ll;
}
-void do_frin (void)
+uint64_t helper_frin (uint64_t arg)
{
- do_fri(float_round_nearest_even);
+ return do_fri(arg, float_round_nearest_even);
}
-void do_friz (void)
+uint64_t helper_friz (uint64_t arg)
{
- do_fri(float_round_to_zero);
+ return do_fri(arg, float_round_to_zero);
}
-void do_frip (void)
+uint64_t helper_frip (uint64_t arg)
{
- do_fri(float_round_up);
+ return do_fri(arg, float_round_up);
}
-void do_frim (void)
+uint64_t helper_frim (uint64_t arg)
{
- do_fri(float_round_down);
+ return do_fri(arg, float_round_down);
}
-#if USE_PRECISE_EMULATION
-void do_fmadd (void)
+/* fmadd - fmadd. */
+uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1) ||
- float64_is_signaling_nan(FT2))) {
+ CPU_DoubleU farg1, farg2, farg3;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
/* sNaN operation */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
#ifdef FLOAT128
/* This is the way the PowerPC specification defines it */
float128 ft0_128, ft1_128;
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ farg1.d = float128_to_float64(ft0_128, &env->fp_status);
#else
/* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) + FT2;
+ farg1.d = (farg1.d * farg2.d) + farg3.d;
#endif
}
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
+#endif
+ return farg1.ll;
}
-void do_fmsub (void)
+/* fmsub - fmsub. */
+uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1) ||
- float64_is_signaling_nan(FT2))) {
+ CPU_DoubleU farg1, farg2, farg3;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
/* sNaN operation */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
#ifdef FLOAT128
/* This is the way the PowerPC specification defines it */
float128 ft0_128, ft1_128;
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ farg1.d = float128_to_float64(ft0_128, &env->fp_status);
#else
/* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) - FT2;
+ farg1.d = (farg1.d * farg2.d) - farg3.d;
#endif
}
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
+#endif
+ return farg1.ll;
}
-#endif /* USE_PRECISE_EMULATION */
-void do_fnmadd (void)
+/* fnmadd - fnmadd. */
+uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1) ||
- float64_is_signaling_nan(FT2))) {
+ CPU_DoubleU farg1, farg2, farg3;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
/* sNaN operation */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
#if USE_PRECISE_EMULATION
#ifdef FLOAT128
/* This is the way the PowerPC specification defines it */
float128 ft0_128, ft1_128;
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ farg1.d= float128_to_float64(ft0_128, &env->fp_status);
#else
/* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) + FT2;
+ farg1.d = (farg1.d * farg2.d) + farg3.d;
#endif
#else
- FT0 = float64_mul(FT0, FT1, &env->fp_status);
- FT0 = float64_add(FT0, FT2, &env->fp_status);
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
#endif
- if (likely(!isnan(FT0)))
- FT0 = float64_chs(FT0);
+ if (likely(!isnan(farg1.d)))
+ farg1.d = float64_chs(farg1.d);
}
+ return farg1.ll;
}
-void do_fnmsub (void)
+/* fnmsub - fnmsub. */
+uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1) ||
- float64_is_signaling_nan(FT2))) {
+ CPU_DoubleU farg1, farg2, farg3;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
/* sNaN operation */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
#if USE_PRECISE_EMULATION
#ifdef FLOAT128
/* This is the way the PowerPC specification defines it */
float128 ft0_128, ft1_128;
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
+ farg1.d = float128_to_float64(ft0_128, &env->fp_status);
#else
/* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) - FT2;
+ farg1.d = (farg1.d * farg2.d) - farg3.d;
#endif
#else
- FT0 = float64_mul(FT0, FT1, &env->fp_status);
- FT0 = float64_sub(FT0, FT2, &env->fp_status);
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
#endif
- if (likely(!isnan(FT0)))
- FT0 = float64_chs(FT0);
+ if (likely(!isnan(farg1.d)))
+ farg1.d = float64_chs(farg1.d);
}
+ return farg1.ll;
}
-#if USE_PRECISE_EMULATION
-void do_frsp (void)
+/* frsp - frsp. */
+uint64_t helper_frsp (uint64_t arg)
{
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ CPU_DoubleU farg;
+ farg.ll = arg;
+
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN square root */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
- FT0 = float64_to_float32(FT0, &env->fp_status);
+ fard.d = float64_to_float32(farg.d, &env->fp_status);
}
+#else
+ farg.d = float64_to_float32(farg.d, &env->fp_status);
+#endif
+ return farg.ll;
}
-#endif /* USE_PRECISE_EMULATION */
-void do_fsqrt (void)
+/* fsqrt - fsqrt. */
+uint64_t helper_fsqrt (uint64_t arg)
{
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ CPU_DoubleU farg;
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN square root */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
/* Square root of a negative nonzero number */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
} else {
- FT0 = float64_sqrt(FT0, &env->fp_status);
+ farg.d = float64_sqrt(farg.d, &env->fp_status);
}
+ return farg.ll;
}
-void do_fre (void)
+/* fre - fre. */
+uint64_t helper_fre (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN reciprocal */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (unlikely(iszero(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(iszero(farg.d))) {
/* Zero reciprocal */
- float_zero_divide_excp();
- } else if (likely(isnormal(FT0))) {
- FT0 = float64_div(1.0, FT0, &env->fp_status);
+ farg.ll = float_zero_divide_excp(1.0, farg.d);
+ } else if (likely(isnormal(farg.d))) {
+ farg.d = float64_div(1.0, farg.d, &env->fp_status);
} else {
- p.d = FT0;
- if (p.i == 0x8000000000000000ULL) {
- p.i = 0xFFF0000000000000ULL;
- } else if (p.i == 0x0000000000000000ULL) {
- p.i = 0x7FF0000000000000ULL;
- } else if (isnan(FT0)) {
- p.i = 0x7FF8000000000000ULL;
- } else if (fpisneg(FT0)) {
- p.i = 0x8000000000000000ULL;
+ if (farg.ll == 0x8000000000000000ULL) {
+ farg.ll = 0xFFF0000000000000ULL;
+ } else if (farg.ll == 0x0000000000000000ULL) {
+ farg.ll = 0x7FF0000000000000ULL;
+ } else if (isnan(farg.d)) {
+ farg.ll = 0x7FF8000000000000ULL;
+ } else if (fpisneg(farg.d)) {
+ farg.ll = 0x8000000000000000ULL;
} else {
- p.i = 0x0000000000000000ULL;
+ farg.ll = 0x0000000000000000ULL;
}
- FT0 = p.d;
}
+ return farg.d;
}
-void do_fres (void)
+/* fres - fres. */
+uint64_t helper_fres (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN reciprocal */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (unlikely(iszero(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(iszero(farg.d))) {
/* Zero reciprocal */
- float_zero_divide_excp();
- } else if (likely(isnormal(FT0))) {
+ farg.ll = float_zero_divide_excp(1.0, farg.d);
+ } else if (likely(isnormal(farg.d))) {
#if USE_PRECISE_EMULATION
- FT0 = float64_div(1.0, FT0, &env->fp_status);
- FT0 = float64_to_float32(FT0, &env->fp_status);
+ farg.d = float64_div(1.0, farg.d, &env->fp_status);
+ farg.d = float64_to_float32(farg.d, &env->fp_status);
#else
- FT0 = float32_div(1.0, FT0, &env->fp_status);
+ farg.d = float32_div(1.0, farg.d, &env->fp_status);
#endif
} else {
- p.d = FT0;
- if (p.i == 0x8000000000000000ULL) {
- p.i = 0xFFF0000000000000ULL;
- } else if (p.i == 0x0000000000000000ULL) {
- p.i = 0x7FF0000000000000ULL;
- } else if (isnan(FT0)) {
- p.i = 0x7FF8000000000000ULL;
- } else if (fpisneg(FT0)) {
- p.i = 0x8000000000000000ULL;
+ if (farg.ll == 0x8000000000000000ULL) {
+ farg.ll = 0xFFF0000000000000ULL;
+ } else if (farg.ll == 0x0000000000000000ULL) {
+ farg.ll = 0x7FF0000000000000ULL;
+ } else if (isnan(farg.d)) {
+ farg.ll = 0x7FF8000000000000ULL;
+ } else if (fpisneg(farg.d)) {
+ farg.ll = 0x8000000000000000ULL;
} else {
- p.i = 0x0000000000000000ULL;
+ farg.ll = 0x0000000000000000ULL;
}
- FT0 = p.d;
}
+ return farg.ll;
}
-void do_frsqrte (void)
+/* frsqrte - frsqrte. */
+uint64_t helper_frsqrte (uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (unlikely(float64_is_signaling_nan(FT0))) {
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN reciprocal square root */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
- } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
/* Reciprocal square root of a negative nonzero number */
- fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
- } else if (likely(isnormal(FT0))) {
- FT0 = float64_sqrt(FT0, &env->fp_status);
- FT0 = float32_div(1.0, FT0, &env->fp_status);
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
+ } else if (likely(isnormal(farg.d))) {
+ farg.d = float64_sqrt(farg.d, &env->fp_status);
+ farg.d = float32_div(1.0, farg.d, &env->fp_status);
} else {
- p.d = FT0;
- if (p.i == 0x8000000000000000ULL) {
- p.i = 0xFFF0000000000000ULL;
- } else if (p.i == 0x0000000000000000ULL) {
- p.i = 0x7FF0000000000000ULL;
- } else if (isnan(FT0)) {
- p.i |= 0x000FFFFFFFFFFFFFULL;
- } else if (fpisneg(FT0)) {
- p.i = 0x7FF8000000000000ULL;
+ if (farg.ll == 0x8000000000000000ULL) {
+ farg.ll = 0xFFF0000000000000ULL;
+ } else if (farg.ll == 0x0000000000000000ULL) {
+ farg.ll = 0x7FF0000000000000ULL;
+ } else if (isnan(farg.d)) {
+ farg.ll |= 0x000FFFFFFFFFFFFFULL;
+ } else if (fpisneg(farg.d)) {
+ farg.ll = 0x7FF8000000000000ULL;
} else {
- p.i = 0x0000000000000000ULL;
+ farg.ll = 0x0000000000000000ULL;
}
- FT0 = p.d;
}
+ return farg.ll;
}
-void do_fsel (void)
+/* fsel - fsel. */
+uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- if (!fpisneg(FT0) || iszero(FT0))
- FT0 = FT1;
+ CPU_DoubleU farg1, farg2, farg3;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+
+ if (!fpisneg(farg1.d) || iszero(farg1.d))
+ return farg2.ll;
else
- FT0 = FT2;
+ return farg2.ll;
}
-void do_fcmpu (void)
+uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
{
- if (unlikely(float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1))) {
+ CPU_DoubleU farg1, farg2;
+ uint32_t ret = 0;
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
/* sNaN comparison */
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
- if (float64_lt(FT0, FT1, &env->fp_status)) {
- T0 = 0x08UL;
- } else if (!float64_le(FT0, FT1, &env->fp_status)) {
- T0 = 0x04UL;
+ if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x08UL;
+ } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x04UL;
} else {
- T0 = 0x02UL;
+ ret = 0x02UL;
}
}
env->fpscr &= ~(0x0F << FPSCR_FPRF);
- env->fpscr |= T0 << FPSCR_FPRF;
+ env->fpscr |= ret << FPSCR_FPRF;
+ return ret;
}
-void do_fcmpo (void)
+uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
{
- if (unlikely(float64_is_nan(FT0) ||
- float64_is_nan(FT1))) {
- if (float64_is_signaling_nan(FT0) ||
- float64_is_signaling_nan(FT1)) {
+ CPU_DoubleU farg1, farg2;
+ uint32_t ret = 0;
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+
+ if (unlikely(float64_is_nan(farg1.d) ||
+ float64_is_nan(farg2.d))) {
+ if (float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d)) {
/* sNaN comparison */
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
POWERPC_EXCP_FP_VXVC);
fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
}
} else {
- if (float64_lt(FT0, FT1, &env->fp_status)) {
- T0 = 0x08UL;
- } else if (!float64_le(FT0, FT1, &env->fp_status)) {
- T0 = 0x04UL;
+ if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x08UL;
+ } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x04UL;
} else {
- T0 = 0x02UL;
+ ret = 0x02UL;
}
}
env->fpscr &= ~(0x0F << FPSCR_FPRF);
- env->fpscr |= T0 << FPSCR_FPRF;
+ env->fpscr |= ret << FPSCR_FPRF;
+ return ret;
}
#if !defined (CONFIG_USER_ONLY)
void do_store_msr (void)
{
- T0 = hreg_store_msr(env, T0);
+ T0 = hreg_store_msr(env, T0, 0);
if (T0 != 0) {
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- do_raise_exception(T0);
+ raise_exception(env, T0);
}
}
#endif
/* XXX: beware: this is false if VLE is supported */
env->nip = nip & ~((target_ulong)0x00000003);
- hreg_store_msr(env, msr);
+ hreg_store_msr(env, msr, 1);
#if defined (DEBUG_OP)
cpu_dump_rfi(env->nip, env->msr);
#endif
__do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
~((target_ulong)0xFFFF0000), 0);
}
-#endif
-#if defined(TARGET_PPC64H)
+
void do_hrfid (void)
{
__do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
#endif
#endif
-void do_tw (int flags)
+void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
{
- if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
- ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
- ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
- ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
- ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
- do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
+ ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
+ ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
+ ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
+ ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
}
}
#if defined(TARGET_PPC64)
-void do_td (int flags)
+void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
{
- if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
- ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
- ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
- ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
- ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
- do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
+ ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
+ ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
+ ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
+ ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
}
#endif
/* PowerPC 601 specific instructions (POWER bridge) */
void do_POWER_abso (void)
{
- if ((uint32_t)T0 == INT32_MIN) {
+ if ((int32_t)T0 == INT32_MIN) {
T0 = INT32_MAX;
- xer_ov = 1;
- xer_so = 1;
- } else {
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
+ } else if ((int32_t)T0 < 0) {
T0 = -T0;
- xer_ov = 0;
+ env->xer &= ~(1 << XER_OV);
+ } else {
+ env->xer &= ~(1 << XER_OV);
}
}
{
uint64_t tmp;
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
} else {
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
{
int64_t tmp;
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
- xer_ov = 1;
- xer_so = 1;
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
} else {
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
env->spr[SPR_MQ] = tmp % T1;
tmp /= (int32_t)T1;
if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
- xer_ov = 1;
- xer_so = 1;
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
} else {
- xer_ov = 0;
+ env->xer &= ~(1 << XER_OV);
}
T0 = tmp;
}
void do_POWER_divs (void)
{
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
} else {
env->spr[SPR_MQ] = T0 % T1;
void do_POWER_divso (void)
{
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
+ if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
+ (int32_t)T1 == 0) {
+ T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
env->spr[SPR_MQ] = 0;
- xer_ov = 1;
- xer_so = 1;
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
} else {
T0 = (int32_t)T0 / (int32_t)T1;
env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
- xer_ov = 0;
+ env->xer &= ~(1 << XER_OV);
}
}
T0 = T1 - T0;
if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
- xer_ov = 1;
- xer_so = 1;
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
} else {
- xer_ov = 0;
+ env->xer &= ~(1 << XER_OV);
}
} else {
T0 = 0;
- xer_ov = 0;
+ env->xer &= ~(1 << XER_OV);
}
}
uint32_t ret;
if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
- ret = -1;
+ ret = UINT32_MAX;
} else {
- ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
- (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
+ ret = (UINT32_MAX >> ((uint32_t)T0)) ^
+ ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
if ((uint32_t)T0 > (uint32_t)T1)
ret = ~ret;
}
env->spr[SPR_MQ] = tmp >> 32;
T0 = tmp;
if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
- xer_ov = 1;
- xer_so = 1;
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
} else {
- xer_ov = 0;
+ env->xer &= ~(1 << XER_OV);
}
}
#if !defined (CONFIG_USER_ONLY)
void do_POWER_rac (void)
{
-#if 0
mmu_ctx_t ctx;
+ int nb_BATs;
/* We don't have to generate many instances of this instruction,
* as rac is supervisor only.
*/
- if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
+ /* XXX: FIX THIS: Pretend we have no BAT */
+ nb_BATs = env->nb_BATs;
+ env->nb_BATs = 0;
+ if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
T0 = ctx.raddr;
-#endif
+ env->nb_BATs = nb_BATs;
}
void do_POWER_rfsvc (void)
__do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
}
-/* PowerPC 601 BAT management helper */
-void do_store_601_batu (int nr)
+void do_store_hid0_601 (void)
{
- do_store_ibatu(env, nr, (uint32_t)T0);
- env->DBAT[0][nr] = env->IBAT[0][nr];
- env->DBAT[1][nr] = env->IBAT[1][nr];
+ uint32_t hid0;
+
+ hid0 = env->spr[SPR_HID0];
+ if ((T0 ^ hid0) & 0x00000008) {
+ /* Change current endianness */
+ env->hflags &= ~(1 << MSR_LE);
+ env->hflags_nmsr &= ~(1 << MSR_LE);
+ env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
+ env->hflags |= env->hflags_nmsr;
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
+ __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
+ }
+ }
+ env->spr[SPR_HID0] = T0;
}
#endif
/* mfrom is the most crazy instruction ever seen, imho ! */
/* Real implementation uses a ROM table. Do the same */
#define USE_MFROM_ROM_TABLE
-void do_op_602_mfrom (void)
+target_ulong helper_602_mfrom (target_ulong arg)
{
- if (likely(T0 < 602)) {
+ if (likely(arg < 602)) {
#if defined(USE_MFROM_ROM_TABLE)
#include "mfrom_table.c"
- T0 = mfrom_ROM_table[T0];
+ return mfrom_ROM_table[T0];
#else
double d;
/* Extremly decomposed:
- * -T0 / 256
- * T0 = 256 * log10(10 + 1.0) + 0.5
+ * -arg / 256
+ * return 256 * log10(10 + 1.0) + 0.5
*/
- d = T0;
+ d = arg;
d = float64_div(d, 256, &env->fp_status);
d = float64_chs(d);
d = exp10(d); // XXX: use float emulation function
d = log10(d); // XXX: use float emulation function
d = float64_mul(d, 256, &env->fp_status);
d = float64_add(d, 0.5, &env->fp_status);
- T0 = float64_round_to_int(d, &env->fp_status);
+ return float64_round_to_int(d, &env->fp_status);
#endif
} else {
- T0 = 0;
+ return 0;
}
}
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
-void do_405_check_ov (void)
-{
- if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
- !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
-}
-
-void do_405_check_sat (void)
-{
- if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
- !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
- /* Saturate result */
- if (T2 >> 31) {
- T0 = INT32_MIN;
- } else {
- T0 = INT32_MAX;
- }
- }
-}
/* XXX: to be improved to check access rights when in user-mode */
void do_load_dcr (void)
if (loglevel != 0) {
fprintf(logfile, "No DCR environment\n");
}
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
} else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
if (loglevel != 0) {
fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
}
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
} else {
T0 = val;
}
if (loglevel != 0) {
fprintf(logfile, "No DCR environment\n");
}
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
} else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
if (loglevel != 0) {
fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
}
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
}
}
T0 = i;
}
-#if defined(TARGET_PPCEMB)
+/*****************************************************************************/
/* SPE extension helpers */
/* Use a table to make this quicker */
static uint8_t hbrev[16] = {
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
}
-#define MASKBITS 16 // Random value - to be fixed
-void do_brinc (void)
+#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
+target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
{
uint32_t a, b, d, mask;
- mask = (uint32_t)(-1UL) >> MASKBITS;
- b = T1_64 & mask;
- a = T0_64 & mask;
- d = word_reverse(1 + word_reverse(a | ~mask));
- T0_64 = (T0_64 & ~mask) | (d & mask);
-}
-
-#define DO_SPE_OP2(name) \
-void do_ev##name (void) \
-{ \
- T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
- (uint64_t)_do_e##name(T0_64, T1_64); \
-}
-
-#define DO_SPE_OP1(name) \
-void do_ev##name (void) \
-{ \
- T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
- (uint64_t)_do_e##name(T0_64); \
+ mask = UINT32_MAX >> (32 - MASKBITS);
+ a = arg1 & mask;
+ b = arg2 & mask;
+ d = word_reverse(1 + word_reverse(a | ~b));
+ return (arg1 & ~mask) | (d & b);
}
-/* Fixed-point vector arithmetic */
-static always_inline uint32_t _do_eabs (uint32_t val)
-{
- if (val != 0x80000000)
- val &= ~0x80000000;
-
- return val;
-}
-
-static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
-{
- return op1 + op2;
-}
-
-static always_inline int _do_ecntlsw (uint32_t val)
+uint32_t helper_cntlsw32 (uint32_t val)
{
if (val & 0x80000000)
- return _do_cntlzw(~val);
- else
- return _do_cntlzw(val);
-}
-
-static always_inline int _do_ecntlzw (uint32_t val)
-{
- return _do_cntlzw(val);
-}
-
-static always_inline uint32_t _do_eneg (uint32_t val)
-{
- if (val != 0x80000000)
- val ^= 0x80000000;
-
- return val;
-}
-
-static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
-{
- return rotl32(op1, op2);
-}
-
-static always_inline uint32_t _do_erndw (uint32_t val)
-{
- return (val + 0x000080000000) & 0xFFFF0000;
-}
-
-static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
-{
- /* No error here: 6 bits are used */
- return op1 << (op2 & 0x3F);
-}
-
-static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
-{
- /* No error here: 6 bits are used */
- return op1 >> (op2 & 0x3F);
-}
-
-static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
-{
- /* No error here: 6 bits are used */
- return op1 >> (op2 & 0x3F);
-}
-
-static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
-{
- return op2 - op1;
-}
-
-/* evabs */
-DO_SPE_OP1(abs);
-/* evaddw */
-DO_SPE_OP2(addw);
-/* evcntlsw */
-DO_SPE_OP1(cntlsw);
-/* evcntlzw */
-DO_SPE_OP1(cntlzw);
-/* evneg */
-DO_SPE_OP1(neg);
-/* evrlw */
-DO_SPE_OP2(rlw);
-/* evrnd */
-DO_SPE_OP1(rndw);
-/* evslw */
-DO_SPE_OP2(slw);
-/* evsrws */
-DO_SPE_OP2(srws);
-/* evsrwu */
-DO_SPE_OP2(srwu);
-/* evsubfw */
-DO_SPE_OP2(subfw);
-
-/* evsel is a little bit more complicated... */
-static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
-{
- if (n)
- return op1;
+ return clz32(~val);
else
- return op2;
-}
-
-void do_evsel (void)
-{
- T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
- (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
-}
-
-/* Fixed-point vector comparisons */
-#define DO_SPE_CMP(name) \
-void do_ev##name (void) \
-{ \
- T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
- T1_64 >> 32) << 32, \
- _do_e##name(T0_64, T1_64)); \
-}
-
-static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
-{
- return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
-}
-static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
-{
- return op1 == op2 ? 1 : 0;
-}
-
-static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
-{
- return op1 > op2 ? 1 : 0;
-}
-
-static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
-{
- return op1 > op2 ? 1 : 0;
-}
-
-static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
-{
- return op1 < op2 ? 1 : 0;
+ return clz32(val);
}
-static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
+uint32_t helper_cntlzw32 (uint32_t val)
{
- return op1 < op2 ? 1 : 0;
+ return clz32(val);
}
-/* evcmpeq */
-DO_SPE_CMP(cmpeq);
-/* evcmpgts */
-DO_SPE_CMP(cmpgts);
-/* evcmpgtu */
-DO_SPE_CMP(cmpgtu);
-/* evcmplts */
-DO_SPE_CMP(cmplts);
-/* evcmpltu */
-DO_SPE_CMP(cmpltu);
-
-/* Single precision floating-point conversions from/to integer */
-static always_inline uint32_t _do_efscfsi (int32_t val)
+/* Single-precision floating-point conversions */
+static always_inline uint32_t efscfsi (uint32_t val)
{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
u.f = int32_to_float32(val, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline uint32_t _do_efscfui (uint32_t val)
+static always_inline uint32_t efscfui (uint32_t val)
{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
u.f = uint32_to_float32(val, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline int32_t _do_efsctsi (uint32_t val)
+static always_inline int32_t efsctsi (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(isnan(u.f)))
return 0;
return float32_to_int32(u.f, &env->spe_status);
}
-static always_inline uint32_t _do_efsctui (uint32_t val)
+static always_inline uint32_t efsctui (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(isnan(u.f)))
return 0;
return float32_to_uint32(u.f, &env->spe_status);
}
-static always_inline int32_t _do_efsctsiz (uint32_t val)
+static always_inline uint32_t efsctsiz (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(isnan(u.f)))
return 0;
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
}
-static always_inline uint32_t _do_efsctuiz (uint32_t val)
+static always_inline uint32_t efsctuiz (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(isnan(u.f)))
return 0;
return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
}
-void do_efscfsi (void)
-{
- T0_64 = _do_efscfsi(T0_64);
-}
-
-void do_efscfui (void)
-{
- T0_64 = _do_efscfui(T0_64);
-}
-
-void do_efsctsi (void)
-{
- T0_64 = _do_efsctsi(T0_64);
-}
-
-void do_efsctui (void)
+static always_inline uint32_t efscfsf (uint32_t val)
{
- T0_64 = _do_efsctui(T0_64);
-}
-
-void do_efsctsiz (void)
-{
- T0_64 = _do_efsctsiz(T0_64);
-}
-
-void do_efsctuiz (void)
-{
- T0_64 = _do_efsctuiz(T0_64);
-}
-
-/* Single precision floating-point conversion to/from fractional */
-static always_inline uint32_t _do_efscfsf (uint32_t val)
-{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
u.f = int32_to_float32(val, &env->spe_status);
tmp = int64_to_float32(1ULL << 32, &env->spe_status);
u.f = float32_div(u.f, tmp, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline uint32_t _do_efscfuf (uint32_t val)
+static always_inline uint32_t efscfuf (uint32_t val)
{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
u.f = uint32_to_float32(val, &env->spe_status);
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
u.f = float32_div(u.f, tmp, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline int32_t _do_efsctsf (uint32_t val)
+static always_inline uint32_t efsctsf (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(isnan(u.f)))
return 0;
return float32_to_int32(u.f, &env->spe_status);
}
-static always_inline uint32_t _do_efsctuf (uint32_t val)
+static always_inline uint32_t efsctuf (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(isnan(u.f)))
return 0;
return float32_to_uint32(u.f, &env->spe_status);
}
-static always_inline int32_t _do_efsctsfz (uint32_t val)
-{
- union {
- int32_t u;
- float32 f;
- } u;
- float32 tmp;
-
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_mul(u.f, tmp, &env->spe_status);
-
- return float32_to_int32_round_to_zero(u.f, &env->spe_status);
+#define HELPER_SPE_SINGLE_CONV(name) \
+uint32_t helper_e##name (uint32_t val) \
+{ \
+ return e##name(val); \
+}
+/* efscfsi */
+HELPER_SPE_SINGLE_CONV(fscfsi);
+/* efscfui */
+HELPER_SPE_SINGLE_CONV(fscfui);
+/* efscfuf */
+HELPER_SPE_SINGLE_CONV(fscfuf);
+/* efscfsf */
+HELPER_SPE_SINGLE_CONV(fscfsf);
+/* efsctsi */
+HELPER_SPE_SINGLE_CONV(fsctsi);
+/* efsctui */
+HELPER_SPE_SINGLE_CONV(fsctui);
+/* efsctsiz */
+HELPER_SPE_SINGLE_CONV(fsctsiz);
+/* efsctuiz */
+HELPER_SPE_SINGLE_CONV(fsctuiz);
+/* efsctsf */
+HELPER_SPE_SINGLE_CONV(fsctsf);
+/* efsctuf */
+HELPER_SPE_SINGLE_CONV(fsctuf);
+
+#define HELPER_SPE_VECTOR_CONV(name) \
+uint64_t helper_ev##name (uint64_t val) \
+{ \
+ return ((uint64_t)e##name(val >> 32) << 32) | \
+ (uint64_t)e##name(val); \
}
+/* evfscfsi */
+HELPER_SPE_VECTOR_CONV(fscfsi);
+/* evfscfui */
+HELPER_SPE_VECTOR_CONV(fscfui);
+/* evfscfuf */
+HELPER_SPE_VECTOR_CONV(fscfuf);
+/* evfscfsf */
+HELPER_SPE_VECTOR_CONV(fscfsf);
+/* evfsctsi */
+HELPER_SPE_VECTOR_CONV(fsctsi);
+/* evfsctui */
+HELPER_SPE_VECTOR_CONV(fsctui);
+/* evfsctsiz */
+HELPER_SPE_VECTOR_CONV(fsctsiz);
+/* evfsctuiz */
+HELPER_SPE_VECTOR_CONV(fsctuiz);
+/* evfsctsf */
+HELPER_SPE_VECTOR_CONV(fsctsf);
+/* evfsctuf */
+HELPER_SPE_VECTOR_CONV(fsctuf);
-static always_inline uint32_t _do_efsctufz (uint32_t val)
+/* Single-precision floating-point arithmetic */
+static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
{
- union {
- int32_t u;
- float32 f;
- } u;
- float32 tmp;
-
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_mul(u.f, tmp, &env->spe_status);
-
- return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_add(u1.f, u2.f, &env->spe_status);
+ return u1.l;
}
-void do_efscfsf (void)
+static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efscfsf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
+ return u1.l;
}
-void do_efscfuf (void)
+static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efscfuf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
+ return u1.l;
}
-void do_efsctsf (void)
+static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctsf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_div(u1.f, u2.f, &env->spe_status);
+ return u1.l;
}
-void do_efsctuf (void)
+#define HELPER_SPE_SINGLE_ARITH(name) \
+uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
+{ \
+ return e##name(op1, op2); \
+}
+/* efsadd */
+HELPER_SPE_SINGLE_ARITH(fsadd);
+/* efssub */
+HELPER_SPE_SINGLE_ARITH(fssub);
+/* efsmul */
+HELPER_SPE_SINGLE_ARITH(fsmul);
+/* efsdiv */
+HELPER_SPE_SINGLE_ARITH(fsdiv);
+
+#define HELPER_SPE_VECTOR_ARITH(name) \
+uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
+{ \
+ return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
+ (uint64_t)e##name(op1, op2); \
+}
+/* evfsadd */
+HELPER_SPE_VECTOR_ARITH(fsadd);
+/* evfssub */
+HELPER_SPE_VECTOR_ARITH(fssub);
+/* evfsmul */
+HELPER_SPE_VECTOR_ARITH(fsmul);
+/* evfsdiv */
+HELPER_SPE_VECTOR_ARITH(fsdiv);
+
+/* Single-precision floating-point comparisons */
+static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctuf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
}
-void do_efsctsfz (void)
+static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctsfz(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
}
-void do_efsctufz (void)
+static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctufz(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
}
-/* Double precision floating point helpers */
-static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
+static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efdtstlt(op1, op2);
+ return efststlt(op1, op2);
}
-static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
+static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efdtstgt(op1, op2);
+ return efststgt(op1, op2);
}
-static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
+static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efdtsteq(op1, op2);
+ return efststeq(op1, op2);
}
-void do_efdcmplt (void)
+#define HELPER_SINGLE_SPE_CMP(name) \
+uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
+{ \
+ return e##name(op1, op2) << 2; \
+}
+/* efststlt */
+HELPER_SINGLE_SPE_CMP(fststlt);
+/* efststgt */
+HELPER_SINGLE_SPE_CMP(fststgt);
+/* efststeq */
+HELPER_SINGLE_SPE_CMP(fststeq);
+/* efscmplt */
+HELPER_SINGLE_SPE_CMP(fscmplt);
+/* efscmpgt */
+HELPER_SINGLE_SPE_CMP(fscmpgt);
+/* efscmpeq */
+HELPER_SINGLE_SPE_CMP(fscmpeq);
+
+static always_inline uint32_t evcmp_merge (int t0, int t1)
{
- T0 = _do_efdcmplt(T0_64, T1_64);
+ return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
}
-void do_efdcmpgt (void)
-{
- T0 = _do_efdcmpgt(T0_64, T1_64);
+#define HELPER_VECTOR_SPE_CMP(name) \
+uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
+{ \
+ return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
}
+/* evfststlt */
+HELPER_VECTOR_SPE_CMP(fststlt);
+/* evfststgt */
+HELPER_VECTOR_SPE_CMP(fststgt);
+/* evfststeq */
+HELPER_VECTOR_SPE_CMP(fststeq);
+/* evfscmplt */
+HELPER_VECTOR_SPE_CMP(fscmplt);
+/* evfscmpgt */
+HELPER_VECTOR_SPE_CMP(fscmpgt);
+/* evfscmpeq */
+HELPER_VECTOR_SPE_CMP(fscmpeq);
-void do_efdcmpeq (void)
+/* Double-precision floating-point conversion */
+uint64_t helper_efdcfsi (uint32_t val)
{
- T0 = _do_efdcmpeq(T0_64, T1_64);
+ CPU_DoubleU u;
+
+ u.d = int32_to_float64(val, &env->spe_status);
+
+ return u.ll;
}
-/* Double precision floating-point conversion to/from integer */
-static always_inline uint64_t _do_efdcfsi (int64_t val)
+uint64_t helper_efdcfsid (uint64_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.f = int64_to_float64(val, &env->spe_status);
+ u.d = int64_to_float64(val, &env->spe_status);
- return u.u;
+ return u.ll;
}
-static always_inline uint64_t _do_efdcfui (uint64_t val)
+uint64_t helper_efdcfui (uint32_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.f = uint64_to_float64(val, &env->spe_status);
+ u.d = uint32_to_float64(val, &env->spe_status);
- return u.u;
+ return u.ll;
}
-static always_inline int64_t _do_efdctsi (uint64_t val)
+uint64_t helper_efdcfuid (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
+ u.d = uint64_to_float64(val, &env->spe_status);
- return float64_to_int64(u.f, &env->spe_status);
+ return u.ll;
}
-static always_inline uint64_t _do_efdctui (uint64_t val)
+uint32_t helper_efdctsi (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(isnan(u.d)))
return 0;
- return float64_to_uint64(u.f, &env->spe_status);
+ return float64_to_int32(u.d, &env->spe_status);
}
-static always_inline int64_t _do_efdctsiz (uint64_t val)
+uint32_t helper_efdctui (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(isnan(u.d)))
return 0;
- return float64_to_int64_round_to_zero(u.f, &env->spe_status);
+ return float64_to_uint32(u.d, &env->spe_status);
}
-static always_inline uint64_t _do_efdctuiz (uint64_t val)
+uint32_t helper_efdctsiz (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(isnan(u.d)))
return 0;
- return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
+ return float64_to_int32_round_to_zero(u.d, &env->spe_status);
}
-void do_efdcfsi (void)
+uint64_t helper_efdctsidz (uint64_t val)
{
- T0_64 = _do_efdcfsi(T0_64);
-}
+ CPU_DoubleU u;
-void do_efdcfui (void)
-{
- T0_64 = _do_efdcfui(T0_64);
-}
+ u.ll = val;
+ /* NaN are not treated the same way IEEE 754 does */
+ if (unlikely(isnan(u.d)))
+ return 0;
-void do_efdctsi (void)
-{
- T0_64 = _do_efdctsi(T0_64);
+ return float64_to_int64_round_to_zero(u.d, &env->spe_status);
}
-void do_efdctui (void)
+uint32_t helper_efdctuiz (uint64_t val)
{
- T0_64 = _do_efdctui(T0_64);
-}
+ CPU_DoubleU u;
-void do_efdctsiz (void)
-{
- T0_64 = _do_efdctsiz(T0_64);
-}
+ u.ll = val;
+ /* NaN are not treated the same way IEEE 754 does */
+ if (unlikely(isnan(u.d)))
+ return 0;
-void do_efdctuiz (void)
-{
- T0_64 = _do_efdctuiz(T0_64);
+ return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
}
-/* Double precision floating-point conversion to/from fractional */
-static always_inline uint64_t _do_efdcfsf (int64_t val)
+uint64_t helper_efdctuidz (uint64_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
- float64 tmp;
+ CPU_DoubleU u;
- u.f = int32_to_float64(val, &env->spe_status);
- tmp = int64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_div(u.f, tmp, &env->spe_status);
+ u.ll = val;
+ /* NaN are not treated the same way IEEE 754 does */
+ if (unlikely(isnan(u.d)))
+ return 0;
- return u.u;
+ return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
}
-static always_inline uint64_t _do_efdcfuf (uint64_t val)
+uint64_t helper_efdcfsf (uint32_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.f = uint32_to_float64(val, &env->spe_status);
+ u.d = int32_to_float64(val, &env->spe_status);
tmp = int64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_div(u.f, tmp, &env->spe_status);
+ u.d = float64_div(u.d, tmp, &env->spe_status);
- return u.u;
+ return u.ll;
}
-static always_inline int64_t _do_efdctsf (uint64_t val)
+uint64_t helper_efdcfuf (uint32_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u.d = uint32_to_float64(val, &env->spe_status);
+ tmp = int64_to_float64(1ULL << 32, &env->spe_status);
+ u.d = float64_div(u.d, tmp, &env->spe_status);
- return float64_to_int32(u.f, &env->spe_status);
+ return u.ll;
}
-static always_inline uint64_t _do_efdctuf (uint64_t val)
+uint32_t helper_efdctsf (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(isnan(u.d)))
return 0;
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u.d = float64_mul(u.d, tmp, &env->spe_status);
- return float64_to_uint32(u.f, &env->spe_status);
+ return float64_to_int32(u.d, &env->spe_status);
}
-static always_inline int64_t _do_efdctsfz (uint64_t val)
+uint32_t helper_efdctuf (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(isnan(u.d)))
return 0;
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u.d = float64_mul(u.d, tmp, &env->spe_status);
- return float64_to_int32_round_to_zero(u.f, &env->spe_status);
+ return float64_to_uint32(u.d, &env->spe_status);
}
-static always_inline uint64_t _do_efdctufz (uint64_t val)
+uint32_t helper_efscfd (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
- float64 tmp;
+ CPU_DoubleU u1;
+ CPU_FloatU u2;
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u1.ll = val;
+ u2.f = float64_to_float32(u1.d, &env->spe_status);
- return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
+ return u2.l;
}
-void do_efdcfsf (void)
+uint64_t helper_efdcfs (uint32_t val)
{
- T0_64 = _do_efdcfsf(T0_64);
-}
+ CPU_DoubleU u2;
+ CPU_FloatU u1;
-void do_efdcfuf (void)
-{
- T0_64 = _do_efdcfuf(T0_64);
-}
+ u1.l = val;
+ u2.d = float32_to_float64(u1.f, &env->spe_status);
-void do_efdctsf (void)
-{
- T0_64 = _do_efdctsf(T0_64);
+ return u2.ll;
}
-void do_efdctuf (void)
+/* Double precision fixed-point arithmetic */
+uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdctuf(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_add(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-void do_efdctsfz (void)
+uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdctsfz(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-void do_efdctufz (void)
+uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdctufz(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-/* Floating point conversion between single and double precision */
-static always_inline uint32_t _do_efscfd (uint64_t val)
+uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
{
- union {
- uint64_t u;
- float64 f;
- } u1;
- union {
- uint32_t u;
- float32 f;
- } u2;
-
- u1.u = val;
- u2.f = float64_to_float32(u1.f, &env->spe_status);
-
- return u2.u;
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_div(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-static always_inline uint64_t _do_efdcfs (uint32_t val)
+/* Double precision floating point helpers */
+uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
{
- union {
- uint64_t u;
- float64 f;
- } u2;
- union {
- uint32_t u;
- float32 f;
- } u1;
-
- u1.u = val;
- u2.f = float32_to_float64(u1.f, &env->spe_status);
-
- return u2.u;
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
}
-void do_efscfd (void)
+uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efscfd(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
}
-void do_efdcfs (void)
+uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdcfs(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
}
-/* Single precision fixed-point vector arithmetic */
-/* evfsabs */
-DO_SPE_OP1(fsabs);
-/* evfsnabs */
-DO_SPE_OP1(fsnabs);
-/* evfsneg */
-DO_SPE_OP1(fsneg);
-/* evfsadd */
-DO_SPE_OP2(fsadd);
-/* evfssub */
-DO_SPE_OP2(fssub);
-/* evfsmul */
-DO_SPE_OP2(fsmul);
-/* evfsdiv */
-DO_SPE_OP2(fsdiv);
-
-/* Single-precision floating-point comparisons */
-static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
+uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efststlt(op1, op2);
+ return helper_efdtstlt(op1, op2);
}
-static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
+uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efststgt(op1, op2);
+ return helper_efdtstgt(op1, op2);
}
-static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
+uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efststeq(op1, op2);
-}
-
-void do_efscmplt (void)
-{
- T0 = _do_efscmplt(T0_64, T1_64);
-}
-
-void do_efscmpgt (void)
-{
- T0 = _do_efscmpgt(T0_64, T1_64);
-}
-
-void do_efscmpeq (void)
-{
- T0 = _do_efscmpeq(T0_64, T1_64);
+ return helper_efdtsteq(op1, op2);
}
-/* Single-precision floating-point vector comparisons */
-/* evfscmplt */
-DO_SPE_CMP(fscmplt);
-/* evfscmpgt */
-DO_SPE_CMP(fscmpgt);
-/* evfscmpeq */
-DO_SPE_CMP(fscmpeq);
-/* evfststlt */
-DO_SPE_CMP(fststlt);
-/* evfststgt */
-DO_SPE_CMP(fststgt);
-/* evfststeq */
-DO_SPE_CMP(fststeq);
-
-/* Single-precision floating-point vector conversions */
-/* evfscfsi */
-DO_SPE_OP1(fscfsi);
-/* evfscfui */
-DO_SPE_OP1(fscfui);
-/* evfscfuf */
-DO_SPE_OP1(fscfuf);
-/* evfscfsf */
-DO_SPE_OP1(fscfsf);
-/* evfsctsi */
-DO_SPE_OP1(fsctsi);
-/* evfsctui */
-DO_SPE_OP1(fsctui);
-/* evfsctsiz */
-DO_SPE_OP1(fsctsiz);
-/* evfsctuiz */
-DO_SPE_OP1(fsctuiz);
-/* evfsctsf */
-DO_SPE_OP1(fsctsf);
-/* evfsctuf */
-DO_SPE_OP1(fsctuf);
-#endif /* defined(TARGET_PPCEMB) */
-
/*****************************************************************************/
/* Softmmu support */
#if !defined (CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
-#define GETPC() (__builtin_return_address(0))
#define SHIFT 0
#include "softmmu_template.h"
{
TranslationBlock *tb;
CPUState *saved_env;
- target_phys_addr_t pc;
+ unsigned long pc;
int ret;
/* XXX: hack to restore env in all cases, even if not called from
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
- pc = (target_phys_addr_t)(unsigned long)retaddr;
+ pc = (unsigned long)retaddr;
tb = tb_find_pc(pc);
if (likely(tb)) {
/* the PC is inside the translated code. It means that we have
cpu_restore_state(tb, env, pc, NULL);
}
}
- do_raise_exception_err(env->exception_index, env->error_code);
+ raise_exception_err(env, env->exception_index, env->error_code);
}
env = saved_env;
}
/* Software driven TLBs management */
/* PowerPC 602/603 software TLB load instructions helpers */
-void do_load_6xx_tlb (int is_code)
+static void helper_load_6xx_tlb (target_ulong new_EPN, int is_code)
{
target_ulong RPN, CMP, EPN;
int way;
way = (env->spr[SPR_SRR1] >> 17) & 1;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
- __func__, (unsigned long)T0, (unsigned long)EPN,
- (unsigned long)CMP, (unsigned long)RPN, way);
+ fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
+ " PTE1 " ADDRX " way %d\n",
+ __func__, T0, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
- ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
+ ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
}
-void do_load_74xx_tlb (int is_code)
+void helper_load_6xx_tlbd (target_ulong EPN)
+{
+ helper_load_6xx_tlb(EPN, 0);
+}
+
+void helper_load_6xx_tlbi (target_ulong EPN)
+{
+ helper_load_6xx_tlb(EPN, 1);
+}
+
+/* PowerPC 74xx software TLB load instructions helpers */
+static void helper_load_74xx_tlb (target_ulong new_EPN, int is_code)
{
target_ulong RPN, CMP, EPN;
int way;
way = env->spr[SPR_TLBMISS] & 0x3;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
- __func__, (unsigned long)T0, (unsigned long)EPN,
- (unsigned long)CMP, (unsigned long)RPN, way);
+ fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
+ " PTE1 " ADDRX " way %d\n",
+ __func__, T0, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
- ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
+ ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
}
+void helper_load_74xx_tlbd (target_ulong EPN)
+{
+ helper_load_74xx_tlb(EPN, 0);
+}
+
+void helper_load_74xx_tlbi (target_ulong EPN)
+{
+ helper_load_74xx_tlb(EPN, 1);
+}
+
static always_inline target_ulong booke_tlb_to_page_size (int size)
{
return 1024 << (2 * size);
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
+ fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
}
#endif
T0 &= 0x3F;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
+ fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
}
#endif
T0 &= 0x3F;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n",
+ fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
__func__, word, T0, T1);
}
#endif
projects / qemu.git / blobdiff