q35: allow dynamic sysbus

[qemu.git] / hw / misc / mst_fpga.c

diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c
index 604be5eafe04431f66366f32d81b747f4890b7d4..a10f0496fec31d5ac0eec4bc0a514e855c5ee398 100644 (file)
--- a/hw/misc/mst_fpga.c
+++ b/hw/misc/mst_fpga.c
@@ -10,6 +10,7 @@
  * Contributions after 2012-01-13 are licensed under the terms of the
  * GNU GPL, version 2 or (at your option) any later version.
  */
+#include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/sysbus.h"
 
@@ -35,25 +36,30 @@
 #define MST_PCMCIA_CD0_IRQ     9
 #define MST_PCMCIA_CD1_IRQ     13
 
+#define TYPE_MAINSTONE_FPGA "mainstone-fpga"
+#define MAINSTONE_FPGA(obj) \
+    OBJECT_CHECK(mst_irq_state, (obj), TYPE_MAINSTONE_FPGA)
+
 typedef struct mst_irq_state{
-       SysBusDevice busdev;
-       MemoryRegion iomem;
-
-       qemu_irq parent;
-
-       uint32_t prev_level;
-       uint32_t leddat1;
-       uint32_t leddat2;
-       uint32_t ledctrl;
-       uint32_t gpswr;
-       uint32_t mscwr1;
-       uint32_t mscwr2;
-       uint32_t mscwr3;
-       uint32_t mscrd;
-       uint32_t intmskena;
-       uint32_t intsetclr;
-       uint32_t pcmcia0;
-       uint32_t pcmcia1;
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+
+    qemu_irq parent;
+
+    uint32_t prev_level;
+    uint32_t leddat1;
+    uint32_t leddat2;
+    uint32_t ledctrl;
+    uint32_t gpswr;
+    uint32_t mscwr1;
+    uint32_t mscwr2;
+    uint32_t mscwr3;
+    uint32_t mscrd;
+    uint32_t intmskena;
+    uint32_t intsetclr;
+    uint32_t pcmcia0;
+    uint32_t pcmcia1;
 }mst_irq_state;
 
 static void
@@ -194,33 +200,31 @@ static int mst_fpga_post_load(void *opaque, int version_id)
        return 0;
 }
 
-static int mst_fpga_init(SysBusDevice *dev)
+static void mst_fpga_init(Object *obj)
 {
-       mst_irq_state *s;
-
-       s = FROM_SYSBUS(mst_irq_state, dev);
+    DeviceState *dev = DEVICE(obj);
+    mst_irq_state *s = MAINSTONE_FPGA(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
-       s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
-       s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
+    s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
+    s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
 
-       sysbus_init_irq(dev, &s->parent);
+    sysbus_init_irq(sbd, &s->parent);
 
-       /* alloc the external 16 irqs */
-       qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
+    /* alloc the external 16 irqs */
+    qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS);
 
-       memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
-                           "fpga", 0x00100000);
-       sysbus_init_mmio(dev, &s->iomem);
-       return 0;
+    memory_region_init_io(&s->iomem, obj, &mst_fpga_ops, s,
+                          "fpga", 0x00100000);
+    sysbus_init_mmio(sbd, &s->iomem);
 }
 
 static VMStateDescription vmstate_mst_fpga_regs = {
-       .name = "mainstone_fpga",
-       .version_id = 0,
-       .minimum_version_id = 0,
-       .minimum_version_id_old = 0,
-       .post_load = mst_fpga_post_load,
-       .fields = (VMStateField []) {
+    .name = "mainstone_fpga",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .post_load = mst_fpga_post_load,
+    .fields = (VMStateField[]) {
                VMSTATE_UINT32(prev_level, mst_irq_state),
                VMSTATE_UINT32(leddat1, mst_irq_state),
                VMSTATE_UINT32(leddat2, mst_irq_state),
@@ -241,17 +245,16 @@ static VMStateDescription vmstate_mst_fpga_regs = {
 static void mst_fpga_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
-    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 
-    k->init = mst_fpga_init;
     dc->desc = "Mainstone II FPGA";
     dc->vmsd = &vmstate_mst_fpga_regs;
 }
 
 static const TypeInfo mst_fpga_info = {
-    .name          = "mainstone-fpga",
+    .name          = TYPE_MAINSTONE_FPGA,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(mst_irq_state),
+    .instance_init = mst_fpga_init,
     .class_init    = mst_fpga_class_init,
 };