SysBusDevice parent_obj;
MemoryRegion mmio;
- CharDriverState *chr;
+ CharBackend chr;
qemu_irq irq;
uint8_t rx_fifo[8];
s->rx_fifo_len--;
uart_update_status(s);
uart_update_irq(s);
- qemu_chr_accept_input(s->chr);
+ qemu_chr_fe_accept_input(&s->chr);
break;
default:
break;
case R_TX:
- if (s->chr)
+ if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(s->chr, &ch, 1);
-
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
+ }
s->regs[addr] = value;
/* hax. */
{
XilinxUARTLite *s = XILINX_UARTLITE(dev);
- if (s->chr)
- qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
+ if (s->chr.chr) {
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
+ uart_event, s, NULL);
+ }
}
static void xilinx_uartlite_init(Object *obj)