* QEMU Floppy disk emulator (Intel 82078)
*
* Copyright (c) 2003, 2007 Jocelyn Mayer
- * Copyright (c) 2008 Hervé Poussineau
+ * Copyright (c) 2008 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
#include "qdev-addr.h"
#include "blockdev.h"
#include "sysemu.h"
-#include "block_int.h"
/********************************************************/
/* debug Floppy devices */
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
struct FDCtrl {
+ MemoryRegion iomem;
qemu_irq irq;
/* Controller state */
QEMUTimer *result_timer;
FDCtrl *fdctrl = opaque;
uint32_t retval;
+ reg &= 7;
switch (reg) {
case FD_REG_SRA:
retval = fdctrl_read_statusA(fdctrl);
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
+ reg &= 7;
switch (reg) {
case FD_REG_DOR:
fdctrl_write_dor(fdctrl, value);
}
}
-static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
-{
- return fdctrl_read(opaque, reg & 7);
-}
-
-static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
-{
- fdctrl_write(opaque, reg & 7, value);
-}
-
-static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
+static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
+ unsigned ize)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
-static void fdctrl_write_mem (void *opaque,
- target_phys_addr_t reg, uint32_t value)
+static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
+ uint64_t value, unsigned size)
{
fdctrl_write(opaque, (uint32_t)reg, value);
}
-static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
- fdctrl_read_mem,
- fdctrl_read_mem,
- fdctrl_read_mem,
-};
-
-static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
- fdctrl_write_mem,
- fdctrl_write_mem,
- fdctrl_write_mem,
-};
-
-static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
- fdctrl_read_mem,
- NULL,
- NULL,
+static const MemoryRegionOps fdctrl_mem_ops = {
+ .read = fdctrl_read_mem,
+ .write = fdctrl_write_mem,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
- fdctrl_write_mem,
- NULL,
- NULL,
+static const MemoryRegionOps fdctrl_mem_strict_ops = {
+ .read = fdctrl_read_mem,
+ .write = fdctrl_write_mem,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
static bool fdrive_media_changed_needed(void *opaque)
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
}
-static void fdctrl_change_cb(void *opaque)
+static void fdctrl_change_cb(void *opaque, bool load)
{
FDrive *drive = opaque;
return fdctrl_connect_drives(fdctrl);
}
+static const MemoryRegionPortio fdc_portio_list[] = {
+ { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
+ { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
+ PORTIO_END_OF_LIST(),
+};
+
static int isabus_fdc_init1(ISADevice *dev)
{
FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
int dma_chann = 2;
int ret;
- register_ioport_read(iobase + 0x01, 5, 1,
- &fdctrl_read_port, fdctrl);
- register_ioport_read(iobase + 0x07, 1, 1,
- &fdctrl_read_port, fdctrl);
- register_ioport_write(iobase + 0x01, 5, 1,
- &fdctrl_write_port, fdctrl);
- register_ioport_write(iobase + 0x07, 1, 1,
- &fdctrl_write_port, fdctrl);
- isa_init_ioport_range(dev, iobase, 6);
- isa_init_ioport(dev, iobase + 7);
+ isa_register_portio_list(dev, iobase, fdc_portio_list, fdctrl, "fdc");
isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
fdctrl->dma_chann = dma_chann;
{
FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
FDCtrl *fdctrl = &sys->state;
- int io;
int ret;
- io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x08, io);
+ memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
+ sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
fdctrl->dma_chann = -1;
- qdev_set_legacy_instance_id(&dev->qdev, io, 2);
+ qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
ret = fdctrl_init_common(fdctrl);
return ret;
static int sun4m_fdc_init1(SysBusDevice *dev)
{
FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
- int io;
- io = cpu_register_io_memory(fdctrl_mem_read_strict,
- fdctrl_mem_write_strict, fdctrl,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x08, io);
+ memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
+ "fdctrl", 0x08);
+ sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
fdctrl->sun4m = 1;
- qdev_set_legacy_instance_id(&dev->qdev, io, 2);
+ qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
return fdctrl_init_common(fdctrl);
}
+void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
+{
+ FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
+ FDCtrl *fdctrl = &isa->state;
+ int i;
+
+ for (i = 0; i < MAX_FD; i++) {
+ bs[i] = fdctrl->drives[i].bs;
+ }
+}
+
+
static const VMStateDescription vmstate_isa_fdc ={
.name = "fdc",
.version_id = 2,
}
};
-static ISADeviceInfo isa_fdc_info = {
- .init = isabus_fdc_init1,
- .qdev.name = "isa-fdc",
- .qdev.fw_name = "fdc",
- .qdev.size = sizeof(FDCtrlISABus),
- .qdev.no_user = 1,
- .qdev.vmsd = &vmstate_isa_fdc,
- .qdev.reset = fdctrl_external_reset_isa,
- .qdev.props = (Property[]) {
+static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
+{
+ ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
+ ic->init = isabus_fdc_init1;
+}
+
+static DeviceInfo isa_fdc_info = {
+ .class_init = isabus_fdc_class_init1,
+ .name = "isa-fdc",
+ .fw_name = "fdc",
+ .size = sizeof(FDCtrlISABus),
+ .no_user = 1,
+ .vmsd = &vmstate_isa_fdc,
+ .reset = fdctrl_external_reset_isa,
+ .props = (Property[]) {
DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
projects / qemu.git / blobdiff