#define SONIC_TCR_CRCI 0x2000
#define SONIC_TCR_PINT 0x8000
+#define SONIC_ISR_RBAE 0x0010
#define SONIC_ISR_RBE 0x0020
#define SONIC_ISR_RDE 0x0040
#define SONIC_ISR_TC 0x0080
/* Hardware */
uint8_t it_shift;
bool big_endian;
+ bool last_rba_is_full;
qemu_irq irq;
#ifdef DEBUG_SONIC
int irq_level;
s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
}
- /* Check resource exhaustion */
+ /* Warn the host if CRBA now has the last available resource */
if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
{
s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
dp8393x_update_irq(s);
}
- /* Done */
- s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
+ /* Allow packet reception */
+ s->last_rba_is_full = false;
}
static void dp8393x_do_software_reset(dp8393xState *s)
dp8393x_update_wt_regs(s);
}
-static int dp8393x_can_receive(NetClientState *nc);
+static bool dp8393x_can_receive(NetClientState *nc);
static void dp8393x_do_receiver_enable(dp8393xState *s)
{
* (4 + 3 * s->regs[SONIC_TFC]),
MEMTXATTRS_UNSPECIFIED, s->data,
size);
- s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1;
- if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) {
+ s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0);
+ if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
/* EOL detected */
break;
}
dp8393x_do_start_timer(s);
if (command & SONIC_CR_RST)
dp8393x_do_software_reset(s);
- if (command & SONIC_CR_RRRA)
+ if (command & SONIC_CR_RRRA) {
dp8393x_do_read_rra(s);
+ s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
+ }
if (command & SONIC_CR_LCAM)
dp8393x_do_load_cam(s);
}
dp8393x_do_read_rra(s);
}
dp8393x_update_irq(s);
- if (dp8393x_can_receive(s->nic->ncs)) {
- qemu_flush_queued_packets(qemu_get_queue(s->nic));
- }
break;
- /* Ignore least significant bit */
+ /* The guest is required to store aligned pointers here */
case SONIC_RSA:
case SONIC_REA:
case SONIC_RRP:
case SONIC_RWP:
- s->regs[reg] = val & 0xfffe;
+ if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
+ s->regs[reg] = val & 0xfffc;
+ } else {
+ s->regs[reg] = val & 0xfffe;
+ }
break;
/* Invert written value for some registers */
case SONIC_CRCT:
dp8393x_update_irq(s);
}
-static int dp8393x_can_receive(NetClientState *nc)
+static bool dp8393x_can_receive(NetClientState *nc)
{
dp8393xState *s = qemu_get_nic_opaque(nc);
- if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
- return 0;
- if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)
- return 0;
- return 1;
+ return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN);
}
static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
dp8393xState *s = qemu_get_nic_opaque(nc);
int packet_type;
uint32_t available, address;
- int width, rx_len = pkt_size;
+ int width, rx_len, padded_len;
uint32_t checksum;
int size;
- width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
-
s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
+ if (s->last_rba_is_full) {
+ return pkt_size;
+ }
+
+ rx_len = pkt_size + sizeof(checksum);
+ if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
+ width = 2;
+ padded_len = ((rx_len - 1) | 3) + 1;
+ } else {
+ width = 1;
+ padded_len = ((rx_len - 1) | 1) + 1;
+ }
+
+ if (padded_len > dp8393x_rbwc(s) * 2) {
+ DPRINTF("oversize packet, pkt_size is %d\n", pkt_size);
+ s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;
+ dp8393x_update_irq(s);
+ s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
+ goto done;
+ }
+
packet_type = dp8393x_receive_filter(s, buf, pkt_size);
if (packet_type < 0) {
DPRINTF("packet not for netcard\n");
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
s->data, size);
- if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) {
+ s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
+ if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
/* Still EOL ; stop reception */
return -1;
- } else {
- s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
}
+ /* Link has been updated by host */
+
+ /* Clear in_use */
+ size = sizeof(uint16_t) * width;
+ address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
+ dp8393x_put(s, width, 0, 0);
+ address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
+ (uint8_t *)s->data, size, 1);
+
+ /* Move to next descriptor */
+ s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
+ s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
}
/* Save current position */
s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
/* Calculate the ethernet checksum */
- checksum = cpu_to_le32(crc32(0, buf, rx_len));
+ checksum = cpu_to_le32(crc32(0, buf, pkt_size));
/* Put packet into RBA */
DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
address = dp8393x_crba(s);
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- buf, rx_len);
- address += rx_len;
+ buf, pkt_size);
+ address += pkt_size;
+
+ /* Put frame checksum into RBA */
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- &checksum, 4);
- rx_len += 4;
+ &checksum, sizeof(checksum));
+ address += sizeof(checksum);
+
+ /* Pad short packets to keep pointers aligned */
+ if (rx_len < padded_len) {
+ size = padded_len - rx_len;
+ address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
+ (uint8_t *)"\xFF\xFF\xFF", size, 1);
+ address += size;
+ }
+
s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff;
available = dp8393x_rbwc(s);
- available -= rx_len / 2;
+ available -= padded_len >> 1;
s->regs[SONIC_RBWC1] = available >> 16;
s->regs[SONIC_RBWC0] = available & 0xffff;
MEMTXATTRS_UNSPECIFIED,
s->data, size);
- /* Move to next descriptor */
+ /* Check link field */
size = sizeof(uint16_t) * width;
address_space_read(&s->as,
dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
dp8393x_put(s, width, 0, 0);
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
s->data, size);
+
+ /* Move to next descriptor */
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
- s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
+ }
+
+ dp8393x_update_irq(s);
+
+ s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |
+ ((s->regs[SONIC_RSC] + 1) & 0x00ff);
- if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
- /* Read next RRA */
+done:
+
+ if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
+ if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
+ /* Stop packet reception */
+ s->last_rba_is_full = true;
+ } else {
+ /* Read next resource */
dp8393x_do_read_rra(s);
}
}
- /* Done */
- dp8393x_update_irq(s);
-
return pkt_size;
}
timer_del(s->watchdog);
memset(s->regs, 0, sizeof(s->regs));
+ s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */
s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
- s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
- memory_region_init_ram(&s->prom, OBJECT(dev),
- "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
+ memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom",
+ SONIC_PROM_SIZE, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- memory_region_set_readonly(&s->prom, true);
prom = memory_region_get_ram_ptr(&s->prom);
checksum = 0;
for (i = 0; i < 6; i++) {
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