* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
*/
#include "sysbus.h"
#include "qemu-timer.h"
+#include "sysemu.h"
//#define DEBUG_PL031
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
QEMUTimer *timer;
qemu_irq irq;
+ /* Needed to preserve the tick_count across migration, even if the
+ * absolute value of the rtc_clock is different on the source and
+ * destination.
+ */
+ uint32_t tick_offset_vmstate;
uint32_t tick_offset;
uint32_t mr;
{
pl031_state *s = (pl031_state *)opaque;
- s->im = 1;
+ s->is = 1;
DPRINTF("Alarm raised\n");
pl031_update(s);
}
static uint32_t pl031_get_count(pl031_state *s)
{
- /* This assumes qemu_get_clock returns the time since the machine was
- created. */
- return s->tick_offset + qemu_get_clock(vm_clock) / get_ticks_per_sec();
+ int64_t now = qemu_get_clock_ns(rtc_clock);
+ return s->tick_offset + now / get_ticks_per_sec();
}
static void pl031_set_alarm(pl031_state *s)
{
- int64_t now;
uint32_t ticks;
- now = qemu_get_clock(vm_clock);
- ticks = s->tick_offset + now / get_ticks_per_sec();
-
/* The timer wraps around. This subtraction also wraps in the same way,
and gives correct results when alarm < now_ticks. */
- ticks = s->mr - ticks;
+ ticks = s->mr - pl031_get_count(s);
DPRINTF("Alarm set in %ud ticks\n", ticks);
if (ticks == 0) {
qemu_del_timer(s->timer);
pl031_interrupt(s);
} else {
+ int64_t now = qemu_get_clock_ns(rtc_clock);
qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
}
}
-static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
+static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
}
static void pl031_write(void * opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
pl031_update(s);
break;
case RTC_ICR:
- /* The PL031 documentation (DDI0224B) states that the interupt is
+ /* The PL031 documentation (DDI0224B) states that the interrupt is
cleared when bit 0 of the written value is set. However the
arm926e documentation (DDI0287B) states that the interrupt is
cleared when any value is written. */
}
}
-static CPUWriteMemoryFunc * const pl031_writefn[] = {
- pl031_write,
- pl031_write,
- pl031_write
-};
-
-static CPUReadMemoryFunc * const pl031_readfn[] = {
- pl031_read,
- pl031_read,
- pl031_read
+static const MemoryRegionOps pl031_ops = {
+ .read = pl031_read,
+ .write = pl031_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl031_init(SysBusDevice *dev)
{
- int iomemtype;
pl031_state *s = FROM_SYSBUS(pl031_state, dev);
struct tm tm;
- iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- if (iomemtype == -1) {
- hw_error("pl031_init: Can't register I/O memory\n");
- }
-
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
- /* ??? We assume vm_clock is zero at this point. */
qemu_get_timedate(&tm, 0);
- s->tick_offset = mktimegm(&tm);
+ s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
- s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s);
+ s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
return 0;
}
-static void pl031_register_devices(void)
+static void pl031_pre_save(void *opaque)
+{
+ pl031_state *s = opaque;
+
+ /* tick_offset is base_time - rtc_clock base time. Instead, we want to
+ * store the base time relative to the vm_clock for backwards-compatibility. */
+ int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
+ s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
+}
+
+static int pl031_post_load(void *opaque, int version_id)
+{
+ pl031_state *s = opaque;
+
+ int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
+ s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
+ pl031_set_alarm(s);
+ return 0;
+}
+
+static const VMStateDescription vmstate_pl031 = {
+ .name = "pl031",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .pre_save = pl031_pre_save,
+ .post_load = pl031_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
+ VMSTATE_UINT32(mr, pl031_state),
+ VMSTATE_UINT32(lr, pl031_state),
+ VMSTATE_UINT32(cr, pl031_state),
+ VMSTATE_UINT32(im, pl031_state),
+ VMSTATE_UINT32(is, pl031_state),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void pl031_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = pl031_init;
+ dc->no_user = 1;
+ dc->vmsd = &vmstate_pl031;
+}
+
+static TypeInfo pl031_info = {
+ .name = "pl031",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(pl031_state),
+ .class_init = pl031_class_init,
+};
+
+static void pl031_register_types(void)
{
- sysbus_register_dev("pl031", sizeof(pl031_state), pl031_init);
+ type_register_static(&pl031_info);
}
-device_init(pl031_register_devices)
+type_init(pl031_register_types)
projects / qemu.git / blobdiff