* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/arm/omap.h"
#include "hw/sysbus.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
/* Interrupt Handlers */
struct omap_intr_handler_bank_s {
unsigned char priority[32];
};
+#define TYPE_OMAP_INTC "common-omap-intc"
+#define OMAP_INTC(obj) \
+ OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
+
struct omap_intr_handler_s {
- SysBusDevice busdev;
+ SysBusDevice parent_obj;
+
qemu_irq *pins;
qemu_irq parent_intr[2];
MemoryRegion mmio;
static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
{
- int i, j, sir_intr, p_intr, p, f;
+ int i, j, sir_intr, p_intr, p;
uint32_t level;
sir_intr = 0;
p_intr = 255;
for (j = 0; j < s->nbanks; ++j) {
level = s->bank[j].irqs & ~s->bank[j].mask &
(is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
- for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
- level >>= f) {
+
+ while (level != 0) {
+ i = ctz32(level);
p = s->bank[j].priority[i];
if (p <= p_intr) {
p_intr = p;
sir_intr = 32 * j + i;
}
- f = ffs(level >> 1);
+ level &= level - 1;
}
}
s->sir_intr[is_fiq] = sir_intr;
static void omap_inth_reset(DeviceState *dev)
{
- struct omap_intr_handler_s *s = FROM_SYSBUS(struct omap_intr_handler_s,
- SYS_BUS_DEVICE(dev));
+ struct omap_intr_handler_s *s = OMAP_INTC(dev);
int i;
for (i = 0; i < s->nbanks; ++i){
qemu_set_irq(s->parent_intr[1], 0);
}
-static int omap_intc_init(SysBusDevice *dev)
+static void omap_intc_init(Object *obj)
{
- struct omap_intr_handler_s *s;
- s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
- if (!s->iclk) {
- hw_error("omap-intc: clk not connected\n");
- }
+ DeviceState *dev = DEVICE(obj);
+ struct omap_intr_handler_s *s = OMAP_INTC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
s->nbanks = 1;
- sysbus_init_irq(dev, &s->parent_intr[0]);
- sysbus_init_irq(dev, &s->parent_intr[1]);
- qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
- memory_region_init_io(&s->mmio, OBJECT(s), &omap_inth_mem_ops, s,
+ sysbus_init_irq(sbd, &s->parent_intr[0]);
+ sysbus_init_irq(sbd, &s->parent_intr[1]);
+ qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, obj, &omap_inth_mem_ops, s,
"omap-intc", s->size);
- sysbus_init_mmio(dev, &s->mmio);
- return 0;
+ sysbus_init_mmio(sbd, &s->mmio);
+}
+
+static void omap_intc_realize(DeviceState *dev, Error **errp)
+{
+ struct omap_intr_handler_s *s = OMAP_INTC(dev);
+
+ if (!s->iclk) {
+ error_setg(errp, "omap-intc: clk not connected");
+ }
}
static Property omap_intc_properties[] = {
static void omap_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = omap_intc_init;
dc->reset = omap_inth_reset;
dc->props = omap_intc_properties;
+ /* Reason: pointer property "clk" */
+ dc->user_creatable = false;
+ dc->realize = omap_intc_realize;
}
static const TypeInfo omap_intc_info = {
.name = "omap-intc",
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(struct omap_intr_handler_s),
+ .parent = TYPE_OMAP_INTC,
+ .instance_init = omap_intc_init,
.class_init = omap_intc_class_init,
};
case 0x10: /* INTC_SYSCONFIG */
s->autoidle &= 4;
s->autoidle |= (value & 1) << 2;
- if (value & 2) /* SOFTRESET */
- omap_inth_reset(&s->busdev.qdev);
+ if (value & 2) { /* SOFTRESET */
+ omap_inth_reset(DEVICE(s));
+ }
return;
case 0x48: /* INTC_CONTROL */
* for every register, see Chapter 3 and 4 for privileged mode. */
if (value & 1)
fprintf(stderr, "%s: protection mode enable attempt\n",
- __FUNCTION__);
+ __func__);
return;
case 0x50: /* INTC_IDLE */
},
};
-static int omap2_intc_init(SysBusDevice *dev)
+static void omap2_intc_init(Object *obj)
+{
+ DeviceState *dev = DEVICE(obj);
+ struct omap_intr_handler_s *s = OMAP_INTC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ s->level_only = 1;
+ s->nbanks = 3;
+ sysbus_init_irq(sbd, &s->parent_intr[0]);
+ sysbus_init_irq(sbd, &s->parent_intr[1]);
+ qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, obj, &omap2_inth_mem_ops, s,
+ "omap2-intc", 0x1000);
+ sysbus_init_mmio(sbd, &s->mmio);
+}
+
+static void omap2_intc_realize(DeviceState *dev, Error **errp)
{
- struct omap_intr_handler_s *s;
- s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
+ struct omap_intr_handler_s *s = OMAP_INTC(dev);
+
if (!s->iclk) {
- hw_error("omap2-intc: iclk not connected\n");
+ error_setg(errp, "omap2-intc: iclk not connected");
+ return;
}
if (!s->fclk) {
- hw_error("omap2-intc: fclk not connected\n");
+ error_setg(errp, "omap2-intc: fclk not connected");
+ return;
}
- s->level_only = 1;
- s->nbanks = 3;
- sysbus_init_irq(dev, &s->parent_intr[0]);
- sysbus_init_irq(dev, &s->parent_intr[1]);
- qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
- memory_region_init_io(&s->mmio, OBJECT(s), &omap2_inth_mem_ops, s,
- "omap2-intc", 0x1000);
- sysbus_init_mmio(dev, &s->mmio);
- return 0;
}
static Property omap2_intc_properties[] = {
static void omap2_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = omap2_intc_init;
dc->reset = omap_inth_reset;
dc->props = omap2_intc_properties;
+ /* Reason: pointer property "iclk", "fclk" */
+ dc->user_creatable = false;
+ dc->realize = omap2_intc_realize;
}
static const TypeInfo omap2_intc_info = {
.name = "omap2-intc",
+ .parent = TYPE_OMAP_INTC,
+ .instance_init = omap2_intc_init,
+ .class_init = omap2_intc_class_init,
+};
+
+static const TypeInfo omap_intc_type_info = {
+ .name = TYPE_OMAP_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap_intr_handler_s),
- .class_init = omap2_intc_class_init,
+ .abstract = true,
};
static void omap_intc_register_types(void)
{
+ type_register_static(&omap_intc_type_info);
type_register_static(&omap_intc_info);
type_register_static(&omap2_intc_info);
}
projects / qemu.git / blobdiff