target/mips: Fix big endian host behavior for interleave MSA instructions

[qemu.git] / crypto / hash.c

diff --git a/crypto/hash.c b/crypto/hash.c
index ac59c63d5f805d90a200d80df15c1ce1308bad16..b97323cf9016f9feba9aa88dcc7f05d717328d25 100644 (file)
--- a/crypto/hash.c
+++ b/crypto/hash.c
@@ -19,7 +19,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qapi/error.h"
 #include "crypto/hash.h"
 #include "hashpriv.h"
 
@@ -48,19 +47,16 @@ int qcrypto_hash_bytesv(QCryptoHashAlgorithm alg,
 {
 #ifdef CONFIG_AF_ALG
     int ret;
-
+    /*
+     * TODO:
+     * Maybe we should treat some afalg errors as fatal
+     */
     ret = qcrypto_hash_afalg_driver.hash_bytesv(alg, iov, niov,
                                                 result, resultlen,
-                                                errp);
+                                                NULL);
     if (ret == 0) {
         return ret;
     }
-
-    /*
-     * TODO:
-     * Maybe we should treat some afalg errors as fatal
-     */
-    error_free(*errp);
 #endif
 
     return qcrypto_hash_lib_driver.hash_bytesv(alg, iov, niov,