static void sun4c_check_interrupts(void *opaque);
-static uint32_t sun4c_intctl_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
{
Sun4c_INTCTLState *s = opaque;
uint32_t ret;
return ret;
}
-static void sun4c_intctl_mem_writeb(void *opaque, a_target_phys_addr addr,
+static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
Sun4c_INTCTLState *s = opaque;
}
};
-static void sun4c_intctl_reset(void *opaque)
+static void sun4c_intctl_reset(DeviceState *d)
{
- Sun4c_INTCTLState *s = opaque;
+ Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);
s->reg = 1;
s->pending = 0;
unsigned int i;
io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
- sun4c_intctl_mem_write, s);
+ sun4c_intctl_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
for (i = 0; i < MAX_PILS; i++) {
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
- vmstate_register(-1, &vmstate_sun4c_intctl, s);
- qemu_register_reset(sun4c_intctl_reset, s);
- sun4c_intctl_reset(s);
+
return 0;
}
.init = sun4c_intctl_init1,
.qdev.name = "sun4c_intctl",
.qdev.size = sizeof(Sun4c_INTCTLState),
+ .qdev.vmsd = &vmstate_sun4c_intctl,
+ .qdev.reset = sun4c_intctl_reset,
};
static void sun4c_intctl_register_devices(void)