* THE SOFTWARE.
*/
-#include "hw.h"
-#include "sun4m.h"
-#include "console.h"
#include "sysbus.h"
//#define DEBUG_IRQ
{
}
-static uint32_t sbi_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
{
SBIState *s = opaque;
uint32_t saddr, ret;
return ret;
}
-static void sbi_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
SBIState *s = opaque;
uint32_t saddr;
sbi_mem_writel,
};
-static void sbi_save(QEMUFile *f, void *opaque)
-{
- SBIState *s = opaque;
- unsigned int i;
-
- for (i = 0; i < MAX_CPUS; i++) {
- qemu_put_be32s(f, &s->intreg_pending[i]);
+static const VMStateDescription vmstate_sbi = {
+ .name ="sbi",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),
+ VMSTATE_END_OF_LIST()
}
-}
-
-static int sbi_load(QEMUFile *f, void *opaque, int version_id)
-{
- SBIState *s = opaque;
- unsigned int i;
-
- if (version_id != 1)
- return -EINVAL;
-
- for (i = 0; i < MAX_CPUS; i++) {
- qemu_get_be32s(f, &s->intreg_pending[i]);
- }
-
- return 0;
-}
+};
-static void sbi_reset(void *opaque)
+static void sbi_reset(DeviceState *d)
{
- SBIState *s = opaque;
+ SBIState *s = container_of(d, SBIState, busdev.qdev);
unsigned int i;
for (i = 0; i < MAX_CPUS; i++) {
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
- sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
+ sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory);
- register_savevm("sbi", -1, 1, sbi_save, sbi_load, s);
- qemu_register_reset(sbi_reset, s);
- sbi_reset(s);
return 0;
}
.init = sbi_init1,
.qdev.name = "sbi",
.qdev.size = sizeof(SBIState),
+ .qdev.vmsd = &vmstate_sbi,
+ .qdev.reset = sbi_reset,
};
static void sbi_register_devices(void)