pcnet_h_reset(&d->state);
}
-static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void lance_mem_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
SysBusPCNetState *d = opaque;
pcnet_ioport_writew(&d->state, addr, val & 0xffff);
}
-static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
SysBusPCNetState *d = opaque;
uint32_t val;
return val & 0xffff;
}
-static CPUReadMemoryFunc * const lance_mem_read[3] = {
- NULL,
- lance_mem_readw,
- NULL,
-};
-
-static CPUWriteMemoryFunc * const lance_mem_write[3] = {
- NULL,
- lance_mem_writew,
- NULL,
+static const MemoryRegionOps lance_mem_ops = {
+ .read = lance_mem_read,
+ .write = lance_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 2,
+ .max_access_size = 2,
+ },
};
static void lance_cleanup(VLANClientState *nc)
SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
PCNetState *s = &d->state;
- s->mmio_index =
- cpu_register_io_memory(lance_mem_read, lance_mem_write, d);
+ memory_region_init_io(&s->mmio, &lance_mem_ops, d, "lance-mmio", 4);
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
- sysbus_init_mmio(dev, 4, s->mmio_index);
+ sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
static SysBusDeviceInfo lance_info = {
.init = lance_init,
.qdev.name = "lance",
+ .qdev.fw_name = "ethernet",
.qdev.size = sizeof(SysBusPCNetState),
.qdev.reset = lance_reset,
.qdev.vmsd = &vmstate_lance,