spice: fix initialization order

[qemu.git] / hw / realview_gic.c

diff --git a/hw/realview_gic.c b/hw/realview_gic.c
index b4ef2ccf3c8526e22468861e8bfa807e435ddcb1..5bc37a7120b1c6c944e1ee3729acc1d832b57467 100644 (file)
--- a/hw/realview_gic.c
+++ b/hw/realview_gic.c
@@ -4,61 +4,71 @@
  * Copyright (c) 2006-2007 CodeSourcery.
  * Written by Paul Brook
  *
  * Copyright (c) 2006-2007 CodeSourcery.
  * Written by Paul Brook
  *

- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.

  */
 
  */
 

-#include "hw.h"
-#include "primecell.h"
+#include "sysbus.h"

 
 

-#define GIC_NIRQ 96
-#define NCPU 1
+typedef struct {
+    SysBusDevice busdev;
+    DeviceState *gic;
+    MemoryRegion container;
+} RealViewGICState;

 
 

-/* Only a single "CPU" interface is present.  */
-static inline int
-gic_get_current_cpu(void)
+static void realview_gic_set_irq(void *opaque, int irq, int level)

 {
 {

-  return 0;
+    RealViewGICState *s = (RealViewGICState *)opaque;
+    qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);

 }
 
 }
 

-#include "arm_gic.c"
-
-static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
+static int realview_gic_init(SysBusDevice *dev)

 {
 {

-    gic_state *s = (gic_state *)opaque;
-    offset -= s->base;
-    return gic_cpu_read(s, gic_get_current_cpu(), offset);
+    RealViewGICState *s = FROM_SYSBUS(RealViewGICState, dev);
+    SysBusDevice *busdev;
+    /* The GICs on the RealView boards have a fixed nonconfigurable
+     * number of interrupt lines, so we don't need to expose this as
+     * a qdev property.
+     */
+    int numirq = 96;
+
+    s->gic = qdev_create(NULL, "arm_gic");
+    qdev_prop_set_uint32(s->gic, "num-cpu", 1);
+    qdev_prop_set_uint32(s->gic, "num-irq", numirq);
+    qdev_init_nofail(s->gic);
+    busdev = sysbus_from_qdev(s->gic);
+
+    /* Pass through outbound IRQ lines from the GIC */
+    sysbus_pass_irq(dev, busdev);
+
+    /* Pass through inbound GPIO lines to the GIC */
+    qdev_init_gpio_in(&s->busdev.qdev, realview_gic_set_irq, numirq - 32);
+
+    memory_region_init(&s->container, "realview-gic-container", 0x2000);
+    memory_region_add_subregion(&s->container, 0,
+                                sysbus_mmio_get_region(busdev, 1));
+    memory_region_add_subregion(&s->container, 0x1000,
+                                sysbus_mmio_get_region(busdev, 0));
+    sysbus_init_mmio(dev, &s->container);
+    return 0;

 }
 
 }
 

-static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
-                          uint32_t value)
+static void realview_gic_class_init(ObjectClass *klass, void *data)

 {
 {

-    gic_state *s = (gic_state *)opaque;
-    offset -= s->base;
-    gic_cpu_write(s, gic_get_current_cpu(), offset, value);
-}
+    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

 
 

-static CPUReadMemoryFunc *realview_gic_cpu_readfn[] = {
-   realview_gic_cpu_read,
-   realview_gic_cpu_read,
-   realview_gic_cpu_read
-};
+    sdc->init = realview_gic_init;
+}

 
 

-static CPUWriteMemoryFunc *realview_gic_cpu_writefn[] = {
-   realview_gic_cpu_write,
-   realview_gic_cpu_write,
-   realview_gic_cpu_write
+static TypeInfo realview_gic_info = {
+    .name          = "realview_gic",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(RealViewGICState),
+    .class_init    = realview_gic_class_init,

 };
 
 };
 

-qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq)
+static void realview_gic_register_types(void)

 {
 {

-    gic_state *s;
-    int iomemtype;
-
-    s = gic_init(base, &parent_irq);
-    if (!s)
-        return NULL;
-    iomemtype = cpu_register_io_memory(0, realview_gic_cpu_readfn,
-                                       realview_gic_cpu_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
-    return s->in;
+    type_register_static(&realview_gic_info);

 }
 }

+
+type_init(realview_gic_register_types)