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[qemu.git] / target-sparc / translate.c

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 046dc0b2e176593f9eeac5745a3f02ebd9394892..cd60c114cd7db6ffa0e9782a9f640c5c2c852140 100644 (file)
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -346,13 +346,6 @@ GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 
-#ifdef ALIGN_7_BUGS_FIXED
-#else
-#ifndef CONFIG_USER_ONLY
-#define gen_op_check_align_T0_7()
-#endif
-#endif
-
 /* moves */
 #ifdef CONFIG_USER_ONLY
 #define supervisor(dc) 0
@@ -361,17 +354,24 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 #endif
 #define gen_op_ldst(name)        gen_op_##name##_raw()
 #else
-#define supervisor(dc) (dc->mem_idx == 1)
+#define supervisor(dc) (dc->mem_idx >= 1)
 #ifdef TARGET_SPARC64
 #define hypervisor(dc) (dc->mem_idx == 2)
-#endif
-#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
+#define OP_LD_TABLE(width)                                              \
+    static GenOpFunc * const gen_op_##width[] = {                       \
+        &gen_op_##width##_user,                                         \
+        &gen_op_##width##_kernel,                                       \
+        &gen_op_##width##_hypv,                                         \
+    };
+#else
 #define OP_LD_TABLE(width)                                              \
     static GenOpFunc * const gen_op_##width[] = {                       \
         &gen_op_##width##_user,                                         \
         &gen_op_##width##_kernel,                                       \
     };
 #endif
+#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
+#endif
 
 #ifndef CONFIG_USER_ONLY
 OP_LD_TABLE(ld);
@@ -2934,9 +2934,7 @@ static void disas_sparc_insn(DisasContext * dc)
                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
                 switch (xop) {
                 case 0x0:       /* load word */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
 #ifndef TARGET_SPARC64
                     gen_op_ldst(ld);
 #else
@@ -2947,15 +2945,13 @@ static void disas_sparc_insn(DisasContext * dc)
                     gen_op_ldst(ldub);
                     break;
                 case 0x2:       /* load unsigned halfword */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
-#endif
                     gen_op_ldst(lduh);
                     break;
                 case 0x3:       /* load double word */
-                    gen_op_check_align_T0_7();
                     if (rd & 1)
                         goto illegal_insn;
+                    gen_op_check_align_T0_7();
                     gen_op_ldst(ldd);
                     gen_movl_T0_reg(rd + 1);
                     break;
@@ -2963,18 +2959,14 @@ static void disas_sparc_insn(DisasContext * dc)
                     gen_op_ldst(ldsb);
                     break;
                 case 0xa:       /* load signed halfword */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
-#endif
                     gen_op_ldst(ldsh);
                     break;
                 case 0xd:       /* ldstub -- XXX: should be atomically */
                     gen_op_ldst(ldstub);
                     break;
                 case 0x0f:      /* swap register with memory. Also atomically */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_movl_reg_T1(rd);
                     gen_op_ldst(swap);
                     break;
@@ -2985,9 +2977,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         goto illegal_insn;
                     if (!supervisor(dc))
                         goto priv_insn;
-#elif CONFIG_USER_ONLY
-                    gen_op_check_align_T0_3();
 #endif
+                    gen_op_check_align_T0_3();
                     gen_ld_asi(insn, 4, 0);
                     break;
                 case 0x11:      /* load unsigned byte alternate */
@@ -3005,9 +2996,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         goto illegal_insn;
                     if (!supervisor(dc))
                         goto priv_insn;
-#elif CONFIG_USER_ONLY
-                    gen_op_check_align_T0_1();
 #endif
+                    gen_op_check_align_T0_1();
                     gen_ld_asi(insn, 2, 0);
                     break;
                 case 0x13:      /* load double word alternate */
@@ -3038,9 +3028,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         goto illegal_insn;
                     if (!supervisor(dc))
                         goto priv_insn;
-#elif CONFIG_USER_ONLY
-                    gen_op_check_align_T0_1();
 #endif
+                    gen_op_check_align_T0_1();
                     gen_ld_asi(insn, 2, 1);
                     break;
                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
@@ -3058,9 +3047,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         goto illegal_insn;
                     if (!supervisor(dc))
                         goto priv_insn;
-#elif CONFIG_USER_ONLY
-                    gen_op_check_align_T0_3();
 #endif
+                    gen_op_check_align_T0_3();
                     gen_movl_reg_T1(rd);
                     gen_swap_asi(insn);
                     break;
@@ -3074,9 +3062,7 @@ static void disas_sparc_insn(DisasContext * dc)
 #endif
 #ifdef TARGET_SPARC64
                 case 0x08: /* V9 ldsw */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_op_ldst(ldsw);
                     break;
                 case 0x0b: /* V9 ldx */
@@ -3084,9 +3070,7 @@ static void disas_sparc_insn(DisasContext * dc)
                     gen_op_ldst(ldx);
                     break;
                 case 0x18: /* V9 ldswa */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_ld_asi(insn, 4, 1);
                     break;
                 case 0x1b: /* V9 ldxa */
@@ -3096,9 +3080,7 @@ static void disas_sparc_insn(DisasContext * dc)
                 case 0x2d: /* V9 prefetch, no effect */
                     goto skip_move;
                 case 0x30: /* V9 ldfa */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_ldf_asi(insn, 4);
                     goto skip_move;
                 case 0x33: /* V9 lddfa */
@@ -3122,16 +3104,12 @@ static void disas_sparc_insn(DisasContext * dc)
                     goto jmp_insn;
                 switch (xop) {
                 case 0x20:      /* load fpreg */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_op_ldst(ldf);
                     gen_op_store_FT0_fpr(rd);
                     break;
                 case 0x21:      /* load fsr */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_op_ldst(ldf);
                     gen_op_ldfsr();
                     break;
@@ -3150,18 +3128,14 @@ static void disas_sparc_insn(DisasContext * dc)
                 gen_movl_reg_T1(rd);
                 switch (xop) {
                 case 0x4:
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_op_ldst(st);
                     break;
                 case 0x5:
                     gen_op_ldst(stb);
                     break;
                 case 0x6:
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
-#endif
                     gen_op_ldst(sth);
                     break;
                 case 0x7:
@@ -3180,9 +3154,7 @@ static void disas_sparc_insn(DisasContext * dc)
                     if (!supervisor(dc))
                         goto priv_insn;
 #endif
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_st_asi(insn, 4);
                     break;
                 case 0x15:
@@ -3201,9 +3173,7 @@ static void disas_sparc_insn(DisasContext * dc)
                     if (!supervisor(dc))
                         goto priv_insn;
 #endif
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_1();
-#endif
                     gen_st_asi(insn, 2);
                     break;
                 case 0x17:
@@ -3239,9 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc)
                     goto jmp_insn;
                 switch (xop) {
                 case 0x24:
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_op_load_fpr_FT0(rd);
                     gen_op_ldst(stf);
                     break;
@@ -3272,9 +3240,7 @@ static void disas_sparc_insn(DisasContext * dc)
                 switch (xop) {
 #ifdef TARGET_SPARC64
                 case 0x34: /* V9 stfa */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     gen_op_load_fpr_FT0(rd);
                     gen_stf_asi(insn, 4);
                     break;
@@ -3284,9 +3250,7 @@ static void disas_sparc_insn(DisasContext * dc)
                     gen_stf_asi(insn, 8);
                     break;
                 case 0x3c: /* V9 casa */
-#ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
-#endif
                     flush_T2(dc);
                     gen_movl_reg_T2(rd);
                     gen_cas_asi(insn);
@@ -3378,17 +3342,8 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
     dc->pc = pc_start;
     last_pc = dc->pc;
     dc->npc = (target_ulong) tb->cs_base;
-#if defined(CONFIG_USER_ONLY)
-    dc->mem_idx = 0;
-    dc->fpu_enabled = 1;
-#else
-    dc->mem_idx = ((env->psrs) != 0);
-#ifdef TARGET_SPARC64
-    dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
-#else
-    dc->fpu_enabled = ((env->psref) != 0);
-#endif
-#endif
+    dc->mem_idx = cpu_mmu_index(env);
+    dc->fpu_enabled = cpu_fpu_enabled(env);
     gen_opc_ptr = gen_opc_buf;
     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
     gen_opparam_ptr = gen_opparam_buf;
@@ -3522,6 +3477,7 @@ void cpu_reset(CPUSPARCState *env)
     env->psrps = 1;
 #ifdef TARGET_SPARC64
     env->pstate = PS_PRIV;
+    env->hpstate = HS_PRIV;
     env->pc = 0x1fff0000000ULL;
 #else
     env->pc = 0;