target-mips: Output CP0.Config2-5 in the register dump

[qemu.git] / target-mips / cpu.c

diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index dd954fc55a10e5a4ce05703a9fa2ca4a14267b4d..98dc94e74b6a7c0c14b3384b3dbbdc80e5ee1741 100644 (file)
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -19,7 +19,9 @@
  */
 
 #include "cpu.h"
+#include "kvm_mips.h"
 #include "qemu-common.h"
+#include "sysemu/kvm.h"
 
 
 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
@@ -87,6 +89,12 @@ static void mips_cpu_reset(CPUState *s)
     tlb_flush(s, 1);
 
     cpu_state_reset(env);
+
+#ifndef CONFIG_USER_ONLY
+    if (kvm_enabled()) {
+        kvm_mips_reset_vcpu(cpu);
+    }
+#endif
 }
 
 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
@@ -128,6 +136,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
 
     cc->has_work = mips_cpu_has_work;
     cc->do_interrupt = mips_cpu_do_interrupt;
+    cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
     cc->dump_state = mips_cpu_dump_state;
     cc->set_pc = mips_cpu_set_pc;
     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
@@ -142,6 +151,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
 #endif
 
     cc->gdb_num_core_regs = 73;
+    cc->gdb_stop_before_watchpoint = true;
 }
 
 static const TypeInfo mips_cpu_type_info = {