/*
* QEMU G364 framebuffer Emulator.
*
- * Copyright (c) 2007-2009 Herve Poussineau
+ * Copyright (c) 2007-2011 Herve Poussineau
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
*/
#include "hw.h"
-#include "mips.h"
#include "console.h"
#include "pixel_ops.h"
-
-//#define DEBUG_G364
-
-#ifdef DEBUG_G364
-#define DPRINTF(fmt, ...) \
-do { printf("g364: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...) do {} while (0)
-#endif
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
+#include "trace.h"
+#include "sysbus.h"
typedef struct G364State {
/* hardware */
uint8_t *vram;
- MemoryRegion vram_region;
- int vram_size;
+ uint32_t vram_size;
qemu_irq irq;
+ MemoryRegion mem_vram;
+ MemoryRegion mem_ctrl;
/* registers */
uint8_t color_palette[256][3];
uint8_t cursor_palette[3][3];
int blanked;
} G364State;
-#define REG_ID 0x000000
-#define REG_BOOT 0x080000
-#define REG_DISPLAY 0x080118
-#define REG_VDISPLAY 0x080150
-#define REG_CTLA 0x080300
-#define REG_TOP 0x080400
-#define REG_CURS_PAL 0x080508
-#define REG_CURS_POS 0x080638
-#define REG_CLR_PAL 0x080800
-#define REG_CURS_PAT 0x081000
-#define REG_RESET 0x180000
+#define REG_BOOT 0x000000
+#define REG_DISPLAY 0x000118
+#define REG_VDISPLAY 0x000150
+#define REG_CTLA 0x000300
+#define REG_TOP 0x000400
+#define REG_CURS_PAL 0x000508
+#define REG_CURS_POS 0x000638
+#define REG_CLR_PAL 0x000800
+#define REG_CURS_PAT 0x001000
+#define REG_RESET 0x100000
#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR 0x00800000
+#define G364_PAGE_SIZE 4096
+
static inline int check_dirty(G364State *s, ram_addr_t page)
{
- return memory_region_get_dirty(&s->vram_region, page, DIRTY_MEMORY_VGA);
+ return memory_region_get_dirty(&s->mem_vram, page, DIRTY_MEMORY_VGA);
}
static inline void reset_dirty(G364State *s,
ram_addr_t page_min, ram_addr_t page_max)
{
- memory_region_reset_dirty(&s->vram_region, page_min,
- page_max + TARGET_PAGE_SIZE - 1,
+ memory_region_reset_dirty(&s->mem_vram,
+ page_min,
+ page_max + G364_PAGE_SIZE - page_min - 1,
DIRTY_MEMORY_VGA);
}
w = 4;
break;
default:
- BADF("unknown host depth %d\n", ds_get_bits_per_pixel(s->ds));
+ hw_error("g364: unknown host depth %d",
+ ds_get_bits_per_pixel(s->ds));
return;
}
page_max = page;
if (x < xmin)
xmin = x;
- for (i = 0; i < TARGET_PAGE_SIZE; i++) {
+ for (i = 0; i < G364_PAGE_SIZE; i++) {
uint8_t index;
unsigned int color;
if (unlikely((y >= ycursor && y < ycursor + 64) &&
ymin = s->height;
ymax = 0;
}
- x += TARGET_PAGE_SIZE;
+ x += G364_PAGE_SIZE;
dy = x / s->width;
x = x % s->width;
y += dy;
- vram += TARGET_PAGE_SIZE;
+ vram += G364_PAGE_SIZE;
data_display += dy * ds_get_linesize(s->ds);
dd = data_display + x * w;
}
- page += TARGET_PAGE_SIZE;
+ page += G364_PAGE_SIZE;
}
done:
{
G364State *s = opaque;
+ qemu_flush_coalesced_mmio_buffer();
+
if (s->width == 0 || s->height == 0)
return;
} else if (s->depth == 8) {
g364fb_draw_graphic8(s);
} else {
- BADF("unknown guest depth %d\n", s->depth);
+ error_report("g364: unknown guest depth %d", s->depth);
}
qemu_irq_raise(s->irq);
int i;
s->blanked = 0;
- for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) {
- memory_region_set_dirty(&s->vram_region, i);
+ for (i = 0; i < s->vram_size; i += G364_PAGE_SIZE) {
+ memory_region_set_dirty(&s->mem_vram, i);
}
}
-static void g364fb_reset(void *opaque)
+static void g364fb_reset(G364State *s)
{
- G364State *s = opaque;
qemu_irq_lower(s->irq);
memset(s->color_palette, 0, sizeof(s->color_palette));
s->top_of_screen = 0;
s->width = s->height = 0;
memset(s->vram, 0, s->vram_size);
- g364fb_invalidate_display(opaque);
+ g364fb_invalidate_display(s);
}
static void g364fb_screen_dump(void *opaque, const char *filename)
uint8_t *data_buffer;
FILE *f;
+ qemu_flush_coalesced_mmio_buffer();
+
if (s->depth != 8) {
- BADF("unknown guest depth %d\n", s->depth);
+ error_report("g364: unknown guest depth %d", s->depth);
return;
}
}
/* called for accesses to io ports */
-static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t g364fb_ctrl_read(void *opaque,
+ target_phys_addr_t addr,
+ unsigned int size)
{
G364State *s = opaque;
uint32_t val;
val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
} else {
switch (addr) {
- case REG_ID:
- val = 0x10; /* Mips G364 */
- break;
case REG_DISPLAY:
val = s->width / 4;
break;
break;
default:
{
- BADF("invalid read at [" TARGET_FMT_plx "]\n", addr);
+ error_report("g364: invalid read at [" TARGET_FMT_plx "]",
+ addr);
val = 0;
break;
}
}
}
- DPRINTF("read 0x%08x at [" TARGET_FMT_plx "]\n", val, addr);
+ trace_g364fb_read(addr, val);
return val;
}
-static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
-{
- uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
- if (addr & 0x2)
- return v >> 16;
- else
- return v & 0xffff;
-}
-
-static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
-{
- uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
- return (v >> (8 * (addr & 0x3))) & 0xff;
-}
-
static void g364fb_update_depth(G364State *s)
{
static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
start = ymin * ds_get_linesize(s->ds);
end = (ymax + 1) * ds_get_linesize(s->ds);
- for (i = start; i < end; i += TARGET_PAGE_SIZE) {
- memory_region_set_dirty(&s->vram_region, i);
+ for (i = start; i < end; i += G364_PAGE_SIZE) {
+ memory_region_set_dirty(&s->mem_vram, i);
}
}
-static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void g364fb_ctrl_write(void *opaque,
+ target_phys_addr_t addr,
+ uint64_t val,
+ unsigned int size)
{
G364State *s = opaque;
- DPRINTF("write 0x%08x at [" TARGET_FMT_plx "]\n", val, addr);
+ trace_g364fb_write(addr, val);
if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
/* color palette */
g364fb_invalidate_display(s);
} else {
switch (addr) {
- case REG_ID: /* Card identifier; read-only */
- case REG_BOOT: /* Boot timing */
- case 0x80108: /* Line timing: half sync */
- case 0x80110: /* Line timing: back porch */
- case 0x80120: /* Line timing: short display */
- case 0x80128: /* Frame timing: broad pulse */
- case 0x80130: /* Frame timing: v sync */
- case 0x80138: /* Frame timing: v preequalise */
- case 0x80140: /* Frame timing: v postequalise */
- case 0x80148: /* Frame timing: v blank */
- case 0x80158: /* Line timing: line time */
- case 0x80160: /* Frame store: line start */
- case 0x80168: /* vram cycle: mem init */
- case 0x80170: /* vram cycle: transfer delay */
- case 0x80200: /* vram cycle: mask register */
- /* ignore */
- break;
- case REG_TOP:
- s->top_of_screen = val;
- g364fb_invalidate_display(s);
- break;
- case REG_DISPLAY:
- s->width = val * 4;
- break;
- case REG_VDISPLAY:
- s->height = val / 2;
- break;
- case REG_CTLA:
- s->ctla = val;
- g364fb_update_depth(s);
- g364fb_invalidate_display(s);
- break;
- case REG_CURS_POS:
- g364_invalidate_cursor_position(s);
- s->cursor_position = val;
- g364_invalidate_cursor_position(s);
- break;
- case REG_RESET:
- g364fb_reset(s);
- break;
- default:
- BADF("invalid write of 0x%08x at [" TARGET_FMT_plx "]\n", val, addr);
- break;
+ case REG_BOOT: /* Boot timing */
+ case 0x00108: /* Line timing: half sync */
+ case 0x00110: /* Line timing: back porch */
+ case 0x00120: /* Line timing: short display */
+ case 0x00128: /* Frame timing: broad pulse */
+ case 0x00130: /* Frame timing: v sync */
+ case 0x00138: /* Frame timing: v preequalise */
+ case 0x00140: /* Frame timing: v postequalise */
+ case 0x00148: /* Frame timing: v blank */
+ case 0x00158: /* Line timing: line time */
+ case 0x00160: /* Frame store: line start */
+ case 0x00168: /* vram cycle: mem init */
+ case 0x00170: /* vram cycle: transfer delay */
+ case 0x00200: /* vram cycle: mask register */
+ /* ignore */
+ break;
+ case REG_TOP:
+ s->top_of_screen = val;
+ g364fb_invalidate_display(s);
+ break;
+ case REG_DISPLAY:
+ s->width = val * 4;
+ break;
+ case REG_VDISPLAY:
+ s->height = val / 2;
+ break;
+ case REG_CTLA:
+ s->ctla = val;
+ g364fb_update_depth(s);
+ g364fb_invalidate_display(s);
+ break;
+ case REG_CURS_POS:
+ g364_invalidate_cursor_position(s);
+ s->cursor_position = val;
+ g364_invalidate_cursor_position(s);
+ break;
+ case REG_RESET:
+ g364fb_reset(s);
+ break;
+ default:
+ error_report("g364: invalid write of 0x%" PRIx64
+ " at [" TARGET_FMT_plx "]", val, addr);
+ break;
}
}
qemu_irq_lower(s->irq);
}
-static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
-
- if (addr & 0x2)
- val = (val << 16) | (old_val & 0x0000ffff);
- else
- val = val | (old_val & 0xffff0000);
- g364fb_ctrl_writel(opaque, addr & ~0x3, val);
-}
-
-static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
-
- switch (addr & 3) {
- case 0:
- val = val | (old_val & 0xffffff00);
- break;
- case 1:
- val = (val << 8) | (old_val & 0xffff00ff);
- break;
- case 2:
- val = (val << 16) | (old_val & 0xff00ffff);
- break;
- case 3:
- val = (val << 24) | (old_val & 0x00ffffff);
- break;
- }
- g364fb_ctrl_writel(opaque, addr & ~0x3, val);
-}
-
static const MemoryRegionOps g364fb_ctrl_ops = {
- .old_mmio = {
- .read = {
- g364fb_ctrl_readb,
- g364fb_ctrl_readw,
- g364fb_ctrl_readl,
- },
- .write = {
- g364fb_ctrl_writeb,
- g364fb_ctrl_writew,
- g364fb_ctrl_writel,
- },
- },
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .read = g364fb_ctrl_read,
+ .write = g364fb_ctrl_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
};
-static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
+static int g364fb_post_load(void *opaque, int version_id)
{
G364State *s = opaque;
- unsigned int i, vram_size;
-
- if (version_id != 1)
- return -EINVAL;
-
- vram_size = qemu_get_be32(f);
- if (vram_size < s->vram_size)
- return -EINVAL;
- qemu_get_buffer(f, s->vram, s->vram_size);
- for (i = 0; i < 256; i++)
- qemu_get_buffer(f, s->color_palette[i], 3);
- for (i = 0; i < 3; i++)
- qemu_get_buffer(f, s->cursor_palette[i], 3);
- qemu_get_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
- s->cursor_position = qemu_get_be32(f);
- s->ctla = qemu_get_be32(f);
- s->top_of_screen = qemu_get_be32(f);
- s->width = qemu_get_be32(f);
- s->height = qemu_get_be32(f);
/* force refresh */
g364fb_update_depth(s);
return 0;
}
-static void g364fb_save(QEMUFile *f, void *opaque)
-{
- G364State *s = opaque;
- int i;
-
- qemu_put_be32(f, s->vram_size);
- qemu_put_buffer(f, s->vram, s->vram_size);
- for (i = 0; i < 256; i++)
- qemu_put_buffer(f, s->color_palette[i], 3);
- for (i = 0; i < 3; i++)
- qemu_put_buffer(f, s->cursor_palette[i], 3);
- qemu_put_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
- qemu_put_be32(f, s->cursor_position);
- qemu_put_be32(f, s->ctla);
- qemu_put_be32(f, s->top_of_screen);
- qemu_put_be32(f, s->width);
- qemu_put_be32(f, s->height);
-}
+static const VMStateDescription vmstate_g364fb = {
+ .name = "g364fb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = g364fb_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
+ VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
+ VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
+ VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
+ VMSTATE_UINT32(cursor_position, G364State),
+ VMSTATE_UINT32(ctla, G364State),
+ VMSTATE_UINT32(top_of_screen, G364State),
+ VMSTATE_UINT32(width, G364State),
+ VMSTATE_UINT32(height, G364State),
+ VMSTATE_END_OF_LIST()
+ }
+};
-int g364fb_mm_init(MemoryRegion *system_memory,
- target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
- qemu_irq irq)
+static void g364fb_init(DeviceState *dev, G364State *s)
{
- G364State *s;
- MemoryRegion *io_ctrl = g_new(MemoryRegion, 1);
-
- s = g_malloc0(sizeof(G364State));
-
- s->vram_size = 8 * 1024 * 1024;
- memory_region_init_ram(&s->vram_region, NULL, "g364fb.vram", s->vram_size);
- s->vram = memory_region_get_ram_ptr(&s->vram_region);
- s->irq = irq;
-
- qemu_register_reset(g364fb_reset, s);
- register_savevm(NULL, "g364fb", 0, 1, g364fb_save, g364fb_load, s);
- g364fb_reset(s);
+ s->vram = g_malloc0(s->vram_size);
s->ds = graphic_console_init(g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
- memory_region_add_subregion(system_memory, vram_base, &s->vram_region);
+ memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
+ memory_region_init_ram_ptr(&s->mem_vram, dev, "vram",
+ s->vram_size, s->vram);
+ memory_region_set_coalescing(&s->mem_vram);
+}
+
+typedef struct {
+ SysBusDevice busdev;
+ G364State g364;
+} G364SysBusState;
- memory_region_init_io(io_ctrl, &g364fb_ctrl_ops, s,
- "g364fb-ctrl", 0x200000);
- memory_region_add_subregion(system_memory, ctrl_base, io_ctrl);
+static int g364fb_sysbus_init(SysBusDevice *dev)
+{
+ G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
+
+ g364fb_init(&dev->qdev, s);
+ sysbus_init_irq(dev, &s->irq);
+ sysbus_init_mmio_region(dev, &s->mem_ctrl);
+ sysbus_init_mmio_region(dev, &s->mem_vram);
return 0;
}
+
+static void g364fb_sysbus_reset(DeviceState *d)
+{
+ G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
+ g364fb_reset(&s->g364);
+}
+
+static SysBusDeviceInfo g364fb_sysbus_info = {
+ .init = g364fb_sysbus_init,
+ .qdev.name = "sysbus-g364",
+ .qdev.desc = "G364 framebuffer",
+ .qdev.size = sizeof(G364SysBusState),
+ .qdev.vmsd = &vmstate_g364fb,
+ .qdev.reset = g364fb_sysbus_reset,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
+ 8 * 1024 * 1024),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static void g364fb_register(void)
+{
+ sysbus_register_withprop(&g364fb_sysbus_info);
+}
+
+device_init(g364fb_register);
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